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Original question:

TAS5825M: What does the first number in I2C Monitor mean?

TAS5825M: Can I know or calculate the current PLL frequency?

Axl Lee
Prodigy 210 points
Part Number: TAS5825M


Register 0x39h indicates whether the PLL is locked or not, and whether the PLL is overrate.

Can I know or calculate the current PLL frequency?

  • 0
    TI__Prodigy 110 points

    Hello Axl,

    The value of the PLL output frequency cannot be directly calculated, but is instead automatically calculated internally based on the function of the DSP and sampling rate.

    BCLK/SCLK is used as the main reference clock, and the sampling frequency detector measures the current sampling rate. With this, it sets internal registers to calculate the PLL rate needed for the DAC and DSP automatically. PLL may overrate due to clock error or clock change (SCLK/LRCLK).

    Hope this helps!

    Regards,

    Prithvi

  • 0 in reply to Prithvi Senthilkumar
    Prodigy 210 points

    Hi Prithvi,

    I want to reproduce the PLL overrate situation to test whether this function works.

    The audio processing mode selects Housekeeping that with the largest sampling rate 192k.

    I/O selects PSIA, all signals (including BCLK) are provided by audio precision.

    And FS set as 512, the calculation result is only 192k * 512 = 98.304M.

    Is any other suggested register settings or techniques to reproduce the PLL overrate?

    Sincerely,

    Axl

  • 0 in reply to Axl Lee
    TI__Prodigy 110 points

    Hi Axl,

    The 5825M only supports FS up to 64, so 512 cannot be used since the device is not rated for that and could cause problems, even if the error bits are set to ignore. So the maximum that is supported is 192k * 64 = 12.288M. 

    May I ask which sampling rate and FS you are planning to use for the device and the purpose for testing the PLL overrate function?

    Best regards,

    Prithvi

  • 0 in reply to Prithvi Senthilkumar
    Prodigy 210 points

    Hi Prithvi,

    I have no plan to use which SR and FS, my purpose is very simple, I just want to reproduce the PLL overrate situation on the TAS5825M, to prove that this detect function is normal and works.

    As I said before, I choose PSIA as the input interface, and input signals are generated by the AP (audio precision).

    In order to make the input BCLK as high as possible, I set SR as 216kHz, FS as 256.

    At this time, the AP output its highest frequency 55.296MHz.

    But 150MHz is still far away.

    So I want to ask if there is any way to help me reproduce the PLL overrate situation on the TAS5825M.

    Sincerely,

    Axl

  • +1 in reply to Axl Lee
    TI__Prodigy 110 points

    Hello Axl,

    We do not have a way to reproduce the PLL overrate situation on the TAS5825M since that error is there to distinguish aliasing issues between the PLL and SCLK, since the max sampling frequency values limit the clock much under 150 MHz.

    Our process flows do not have a way to consistently replicate this aliasing.

    As mentioned before, the device is not rated to handle sampling rates above 192k and clock frequencies over 64 FS, so it is not recommended to go past this limit for PLL testing purposes.

    Hope this clarifies your question.

    Best regards,

    Prithvi