PCM1864: Configuration of Master Mode with ADC non-audio MCK

Sadanori Kato

Part Number: PCM1864

Hi,

Could you please tell me how to set the clock divider configuration of master mode with ADC non-audio MCK as the following conditions?

<Example Conditions>
- Mode = Master Mode with ADC non-audio MCK
- PLL = Enable(CLKDET_EN is set to 0)
- Word Length = 24bits
- SCKI = 13.312MHz(Fs x 256)
- BCK = 3.328MHZ(Fs x 64)
- LRCK = 52kHz

Additionally, I referred to the red frame in the following tables. Is it possible to apply this divider setting?

Best regards,
Kato

over 3 years ago

+1 Jeff McPherson over 3 years ago

TI__Mastermind 47485 points

Hi Kato,

The settings in red won't work because you will be violating the 100Mhz limit of the PLL output. I've attached a spreadsheet with some settings you should try. It also functions as a calculator in case your system requirements need to change: 2210.PCM186xPLLCalculator.xlsx

Best regards,

Jeff

0 Sadanori Kato over 3 years ago in reply to Jeff McPherson

Guru 36540 points

Hi Jeff-san,

Thank you for sharing the pll calculation tool.

I understand.

Best regards,
Kato

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PCM1864: Configuration of Master Mode with ADC non-audio MCK