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TLV320AIC3101: Noise issue on Recording audio file - tlv320aic3101

Abhiram A
Prodigy 60 points
Part Number: TLV320AIC3101


Hi Team,

We are using tlv320aic3101 audio codec with a qualcomm processor. We are setting the processor as Master and the codec as slave.
Our MCLK frequency is 6.144Mhz and Bclk 1.53Mhz and Word Select 48 Khz. We are using the pll for adjusting clk in slave side. 


The normal audio is playing without any noise. But the recorded file having some noise amplified situation [The speech is clear but their is some noise in the audio] . Could you please help to find the root cause to solve this issue?

We are using the command "arecord -D hw:0,1 -r 48000 -f S16_LE -c 2 result.wav" for recording. 


For your information, We are giving mic input only through MIC2R/LINE2R .This pin is connected to MICBIAS through a 1k ohm resistor as per our design. Also I am mentioning the registers and data s we are writing for enabling recording path. Also attached one recorded sample.

 

#Register 25: MICBIAS
25 0x40

#Register 12: Audio Codec Digital Filter
12 0xA0

#Register 15: Left-ADC PGA Gain
15 0x80

#Register 16: Right-ADC PGA Gain
16 0x77

#Register 17: MIC2L/R to Left-ADC
 17 0xFF

#Register 18: MIC2/LINE2 to Right-ADC
18 0xF0

#Register 19: MIC1LP/LINE1LP to Left-ADC
19 0x78

#Register 21: MIC1RP/LINE1RP to Left-ADC Control Register
21 0x78

#Register 22: MIC1RP/LINE1RP to Right-ADC Control Register
22 0x7C

#Register 24: MIC1LP/LINE1LP to Right-ADC Control Register
24 0x78

#Register 26: Left-AGC Control
26 0x00

#Register 29: Right-AGC Control
29 0x00

#Register 27: Left-AGC Control
27 0x00

#Register 30: Right-AGC Control
30 0x00

#Register 32: Left-AGC Gain
32 0xEe

#Register 33: Right-AGC Gain
33 0xE8

#Register 36: ADC Flag Register
36 0x9D








  • 0
    TI__Mastermind 29765 points

    Hi,

    Can you provide your PLL configuration setting?

    Did you hear the same noise if you use the bypass mode from MIC2R directly to an output say HP or LINE?

    Regards.

  • 0 in reply to pdjuandi
    Prodigy 60 points

    Hi pdjuandi,

    I am sharing the configuration of pll registers for 6.144 MHZ

    Register 3: PLL Programming Register A ie; Q = 16, P = 1

    3 0x81

    Register 4: PLL Programming Register B ie; J = 16
    4 0x40

    Register 5: PLL Programming Register C (1)
    5 0x00

    Register 6: PLL Programming Register D
    6 0x00

    Register 11: Audio Codec Overflow Flag Register R = 1
    11 0x81

    "Did you hear the same noise if you use the bypass mode from MIC2R directly to an output say HP or LINE?"
    Ans<< No actually , but we have an optional speaker which can be connected to HPLCOM and HPRCOM of the codec.

    Could you please suggest the register configurations for the same?

    For your information, I am attaching the section of the scheme.




    Regards,
    Abhiram

  • 0 in reply to Abhiram A
    TI__Mastermind 29765 points

    Hi,

    Here is a block diagram of this device with its respective register. 

    The register settings look correct, likely issue is on your setup or board.

    Your audio jack connection is based on CTIA standard, are you using the correct plug?

    Try to isolate maybe start with a pure sine tone from your setup without MIC etc.

    Regards.