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TLV320AIC3204: Correct clock settings

Zachary Williams
Prodigy 80 points

Part Number: TLV320AIC3204

Hey all,

I'm attempting to get our codec working with a 12MHz crystal. We only have MCLK connected for our application. Is it possible to configure the TLV320AIC3204 with a 12MHz clock or do we need to configure it for 11.2896MHz or 12.288MHz?

I've included our schematic of the codec integration. Would anyone be able to help with checking to make sure we have things setup correctly and possibly help with correct register settings for this setup?

Thanks!

codec-schematic.pdf

  • 0
    TI__Mastermind 29180 points

    Hi,

    Apologies for the delay, please wait at least 24 hours for our codec expert to respond to your question.

    Thank you for your patience.

  • 0 in reply to Daveon Douglas
    Prodigy 80 points

    Thanks .

    I think we may have figured it out, but we haven't tested it yet. We will be testing tomorrow.

    Per table 2-27 on page 78 of the Application Reference Guide (www.ti.com/.../slaa557.pdf), these are the settings we have for a 44.1 kHz sample rate:

    ###############################################
    # Clock Settings for ADC
    # ---------------------------------------------
    # The codec receives: MCLK = 12 MHz
    # 44.1 kHz sample rate
    ###############################################
    #
    # Select Page 0
    w 30 00 00
    #
    # Register 6 - PLL J = 7
    w 30 06 07
    #
    # Register 7 - PLL D = 560
    w 30 07 02 30
    #
    # Register 18 - NADC = 3, MADC = 5
    w 30 12 83 85
    #
    ###############################################

    ###############################################
    # Clock Settings for DAC
    # ---------------------------------------------
    # The codec receives: MCLK = 12 MHz
    # 44.1 kHz sample rate
    ###############################################
    #
    # Select Page 0
    w 30 00 00
    #
    # Register 11 - NDAC = 5, MDAC = 3
    w 30 0B 85 83
    #
    # Register 13 - DOSR = 128
    w 30 0D 00 80
    #
    ###############################################

  • 0 in reply to Zachary Williams
    TI__Mastermind 29775 points

    Hi,

    My comment on the schematic:

    • I don't see WCLK/BCLK connection to the host though DIN/DOUT is connected to some kind of DSP, is the DSP host then you need to synchronize the MCLK to the clock in the DSP. See this apps. note for more information especially when XTAL is used.

    https://www.ti.com/lit/an/slaa469a/slaa469a.pdf?ts=1663257242149&ref_url=https%253A%252F%252Fwww.ti.com%252Fproduct%252FTLV320AIC3204

    • I don't see pullup for I2C lines, just cross check if this is needed or not.
    • The analog input nets for IN1 and IN2 are swapped with the codec pins, just cross check.
    • Recommend use 2.2K on R65/66/67/68
    • Normally in audio jack TRRS the connections are Left audio, Right audio, MIC and GND, so cross check if this is the intended application.
    • Place AC coupled cap on IN3 lines.
    • Please look at the proposed power sequencing in this apps. note.

    https://www.ti.com/lit/an/slaa492a/slaa492a.pdf?ts=1663260343219

    • Link to the EVM schematic, maybe that will help.

    https://www.ti.com/lit/ug/slau266a/slau266a.pdf?ts=1663257667247&ref_url=https%253A%252F%252Fwww.ti.com%252Ftool%252FTLV320AIC3204EVM-K

    On the configuration:

    • Cross check page 0 register 4, 5 as well to ensure the clock path and PLL is enabled and ratio is correct
    • These should corrected: MADC=3, NADC=5
    • Refer to chapter 4 for examples.

    Regards.

  • 0 in reply to pdjuandi
    Prodigy 140 points

    I'm working with Zach on this project.

    The codec is not connected to any DSP.  The net names with "DSP" in the name are because we are considering the codec as a DSP of sorts.  The only other processor in the system is a microcontroller that talks to the codec via the I2C bus.

    We do need to know however:

    - Do we need to drive the WCLK/BCLK lines given that we are NOT talking to another DSP or processor?

    Aside from that, addressing your concerns:

    - we do have I2C pullups on another page

    - we'll use 2.2K going forward

    - we have custom MIC/Audio input cabling, 

    - IN3 lines are AC coupled on another page

    - Our 1.8V and 3.3V supplies both come up at the same time.

    - We have changed MDAC/MADC = 3, NDAC/NADC = 5

    Thanks,

    Carlos

  • 0 in reply to Carlos17153
    Prodigy 80 points

    I've attached our current log of what is getting written to the codec. , do you see anything problematic? We did notice that when trying to calculate the clock settings, PLLD seemed to need to be 56 instead of 560 for 44.1 kHz sample rate. We've tried both but with the current configuration we are still not getting any output on the line outs.

    Fullscreen AuraLog_Single Ended Loopback IN1 Test w HP OUT V2 2022-09-16.log Download 
    Aura V0.06 Starting up
----DEBUG-MODE-ON----
Applied DSP HARDWARE reset
Released DSP HARDWARE reset
W 0x00 0x00 (Write PAGE reg)
W 0x01 0x01 (write register)  		CODEC:  Did SW Reset
W 0x00 0x00 (Write PAGE reg)
W 0x35 0x14 0x04 (write register)  	CODEC:  DOUT=GPO, DIN=GPI
W 0x37 0x08 0x04 (write register)  	CODEC:  MISO is INT1out, SCLK is GPI
W 0x3C 0x08 (write register)  		CODEC:  DAC signal processing block
W 0x06 0x07 (write register)  		CODEC:  Register 6 - PLL J = 7
W 0x07 0x00 0x38 (write register)  	CODEC:  Register 7 - PLL D = 56 (NOT 560)
W 0x12 0x85 0x83 (write register)  	CODEC:  Register 18 - NADC = 5, MADC = 3
W 0x1D 0x30 (write register)  		CODEC:  Enabled loopback register 29
W 0x3D 0x01 (write register)  		CODEC:  Set the ADC Mode to PRB_R1
W 0x00 0x01 (Write PAGE reg)
W 0x01 0x08 (write register)  		CODEC:  Set Disable weak AVDD
W 0x02 0x00 (write register)  		CODEC:  Enable Master Analog Power Control
W 0x3D 0x00 (write register)  		CODEC:  Select ADC PTM_R4
W 0x47 0x32 (write register)  		CODEC:  Set the input  powerup time
W 0x7B 0x01 (write register)  		CODEC:  Set the REF charging time
W 0x34 0x08 (write register)  		CODEC:  # Route IN1L to LEFT_P
W 0x36 0x80 (write register)  		CODEC:  CM1L to LEFT_M
W 0x37 0x08 (write register)  		CODEC:  Route IN1R to  RIGHT_P 
W 0x39 0x80 (write register)  		CODEC:  Route CM1R to RIGHT_M
W 0x3B 0x0C (write register)  		CODEC:  Unmute Left MICPGA
W 0x3C 0x0C (write register)  		CODEC:  Unmute Right MICPGA
W 0x00 0x00 (Write PAGE reg)
W 0x51 0xC0 (write register)  		CODEC:  Power up LADC/RADC
W 0x52 0x00 (write register)  		CODEC:  Unmute LADC/RADC
W 0x0B 0x85 0x83 (write register)  	CODEC:  Register 11 - NDAC = 5, MDAC = 3
W 0x0D 0x00 0x80 (write register)  	CODEC:  Register 13/14 - DOSR = 128
W 0x3C 0x08 (write register)  		CODEC:  Set  DAC Mode to PRB_P8
W 0x00 0x2C (Write PAGE reg)		
W 0x01 0x04 (write register)  		CODEC:  Enable Adaptivee filtering
W 0x0C 0x7E 0x33 0xA8 0x00 0xC0 0xE6 0x2C 0x00 0x00 0x00 0x00 0x00 0x3E 0x33 0xA9 0x00 0x00 0x00 0x00 0x00 (write register)  CODEC:  Buf A Biquad A, Left Channel
W 0x00 0x2D (Write PAGE reg)
W 0x14 0x7E 0x33 0xA8 0x00 0xC0 0xE6 0x2C 0x00 0x00 0x00 0x00 0x00 0x3E 0x33 0xA9 0x00 0x00 0x00 0x00 0x00 (write register)  CODEC:  Buf A Biquad A, Right Channel
W 0x00 0x2C (Write PAGE reg)
W 0x48 0x7F 0xFF 0xFF 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 (write register)  CODEC:  Buf A Biquad D, Left Channel
W 0xx00 0x2D (Write PAGE reg)
W 0x50 0x7F 0xFF 0xFF 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 (write register)  CODEC:  Buf A Biquad D, Right Channel
W 0x00 0x3E (Write PAGE reg)
W 0x0C 0x7E 0x33 0xA8 0x00 0xC0 0xE6 0x2C 0x00 0x00 0x00 0x00 0x00 0x3E 0x33 0xA9 0x00 0x00 0x00 0x00 0x00 (write register)  CODEC:  Buf B Biquad A, Left Channel
W 0x00 0x3F (Write PAGE reg)
W 0x14 0x7E 0x33 0xA8 0x00 0xC0 0xE6 0x2C 0x00 0x00 0x00 0x00 0x00 0x3E 0x33 0xA9 0x00 0x00 0x00 0x00 0x00 (write register)  CODEC:  Buf B Biquad A,, Right Channel
W 0x00 0x3E (Write PAGE reg)
W 0x48 0x7F 0xFF 0xFF 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 (write register)  CODEC:  Buf B Biquad D, Left Channel
W 0x00 0x3F (Write PAGE reg)
W 0x50 0x7F 0xFF 0xFF 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 (write register)  CODEC:  Buf B Biquad DD, Right Channell
W 0x00 0x01 (Write PAGE reg)
W 0x14 0x25 (write register)   		CODEC:  De-pop
W 0x0C 0x08 0x08 (write register)  	CODEC:  LDAC/RDAC to HPL/HPR
W 0x0E 0x08 0x08 (write register)  	CODEC:  LDAC/RDAC to LOL/LOR
W 0x09 0x3C (write register)  		CODEC:  Power up HPL/HPR and LOL/LOR drivers
W 0x10 0x00 0x00 (write register)  	CODEC:  Unmute HPL/HPR driver, 0dB Gain
W 0x12 0x00 0x00 (write register)  	CODEC:   Unmute LOL/LOR driver, 0ddB Gain
W 0xx00 0x00 (Write PAGE reg)
W 0x41 0x00 0x00 (write register)  	CODEC:  DAC => 0dB
W 0x3F 0xD6 (write register)  		CODEC:  Power up LDAC/RDAC
W 0x40 0x00 (write register)   		CODEC:  Unmute LDAC/RDACCODEC:  INIT DONE

Reading Codec Page 0:
ADDR  0  1  2  3  4  5  6  7   8  9  A  B  C  D  E  F
0x0_ 00 00 60 00 00 11 07 00  38 00 00 85 83 00 80 02
0x1_ 00 08 85 83 80 01 00 04  00 00 01 00 00 30 01 00
0x2_ 00 00 00 00 44 EE 00 00  00 00 00 00 00 00 00 00
0x3_ 00 00 00 00 00 14 05 08  05 00 00 00 08 01 00 D6
0x4_ 00 00 00 00 6F 38 00 00  00 00 00 EE 10 D8 7E E3
0x5_ 00 C0 00 00 00 00 00 00  7F 00 00 00 00 00 00 00
0x6_ 7F 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00
Done reading page 0

Reading Codec Page 1:
ADDR  0  1  2  3  4  5  6  7   8  9  A  B  C  D  E  F
0x0_ 01 08 00 00 00 00 00 00  00 3C 00 10 08 08 08 08
0x1_ 00 00 00 00 25 00 00 00  00 00 00 00 00 00 00 00
0x2_ 00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00
0x3_ 00 00 00 00 08 00 80 08  00 80 00 0C 0C 00 03 F0
0x4_ 00 00 00 00 00 00 00 32  00 00 00 00 00 00 00 00
0x5_ 00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00
0x6_ 00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00
0x7_ 00 00 00 00 00 00 00 00  00 00 00 01 00 00 00 00
Done reading page 1

  • 0 in reply to Zachary Williams
    Prodigy 140 points

    Actually, that was an old log.  The current commands we're sending and the values read back are shown here:

    Aura V0.06 Starting up
----DEBUG-MODE-ON----
Applied DSP HARDWARE reset
Released DSP HARDWARE reset

W 0x00 0x00 (Write PAGE reg)
W 0x01 0x01 (write register)  COODEC:  Did SW Reset
W 0x00 0x00 (Write PAGE reg)
W 0x34 0x18 (write register)  CODEC:  GPIO output is INT2
W 0x35 0x14 0x04 (write registter)  CODEC:  DOUT=GPO, DIN=GPI
W 0x37 0x08 0x04 (write register)  CODEC:  MISO is INT1out, SCLK is GPI
W 0x06 0x07 (write register)  COODEC:  Register 6 - PLL J = 7
W 0x07 0x00 0x38 (write register)  CODEC:  Register 7 - PLL D = 56 (NOT  560)
W 0x12 0x85 0x83 (write register)  CODEC:  Register 18 -  NADC = 5, MADC = 3
W 0x1D 0x00 (write register)  CODEC:   (DAN) DISabled loopback register 29
W 0x3D 0x01 (write register)  CODEC:  Set the ADC Mode to PRB_R1
W 0x00 0x01 (Write PAGE reg)
W 0x01 0x08 (write register)  CODEC:  Set Disable weak AVDD
W 0x02 0xF0 (write register)  CODEC:   (Dan) DISable Master Analog Power Control
W 0x3D 0x00 (write register)  CODEC:   Select ADC PTM_R4
W 0x47 0x32 (write register)  CODEC:  Set the input powerup time
W 0x7B 0x01 (write register)  CODEC:  Set the REF chharging time
W 0x34 0x28 (write register)  CODEC:  (Dan) Route IN2L, IN3L to LPGA+
W 0x36 0x20 (write register)  CODEC:  (Dan) IN2R to LPGA-
W 0x37 0x88 (write register)  CODEC:  (Dan) Route IN1R, IN3R to RPGA+
W 0x39 0x20 (write register)  CODEC:  Route IN1L to RPGA-
W 0x3B 0x0C (write register)  CODEC:  Unmute Left MICPGA
W 0x3C 0x0C (write register)  CODEC:  Unmute Right MICPGA
W 0x00 0x00 (Write PAGE reg)
W 0x51 0xC0 (write register)  CODEC:  Power up LADC/RADC
W 0x52 0x00 (write register)  CODEC:  Unmute LADC/RADC
W 0x0B 0x85 0x83 (write register)  CODEC:  Register 11 - NDAC = 5, MDAC = 3
W 0x0D 0x00 0x80 (write register)  CODEC:  Register 13/14 - DOSR = 128
W 0x3C 0x01 (write register)  CODEC:  (Dan) DAC signal processing bblock
W 0x00 0x2C (Write PAGE reg)
W 0x01 0x04 (write register)  CODEC:  Enable Adaptive filtering
W 0x0C 0x7E 0x33 0xA8 0x00 0xC0 0xE6 0x2C 0x00 0x00 0x00 0x00 0x00 0x3E 0x33 0xA9 0x00 0x00 0x00 0x00 0x00 (write register)  CODEC:  Buf A Biquad A, Left Channel
W 0x00 0x2D (Write PAGE reg)
W 0x14 0x7E 0x33 0xA8 0x00 0xC0 0xE6 0x2C 0x00 0x00 0x00 0x00 0x00 0x3E 0x33 0xA9 0x00 0x00 0x00 0x00 0x00 (write register)  CODEC:  Buf A Biquad A, Right Channel
W 0x00 0x2C (Write PAGE reg)
W 0x48 0x7F 0xFF 0xFF 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 (write register)  CODEC:  Buf A Biquad D, Left Channel
W 0x00 0x2D (Write PAGE reg)
W 0x50 0x7F 0xFF 0xFF 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 (write register)  CODEC:  Buf A Biquad D, Right Channel
W 0x00 0x3E (Write PAGE reg)
W 0x0C 0x7E 0x33 0xA8 0x00 0xC0 0xE6 0x2C 0x00 0x00 0x00 0x00 0x00 0x3E 0x33 0xA9 0x00 0x00 0x00 0x00 0x00 (write register)  CODEC:  Buf B Biquad A, Left Channel
W 0x00 0x3F (Write PAGE reg)
W 0x14 0x7E 0x33 0xA8 0x00 0xC0 0xE6 0x2C 0x00 0x00 0x00 0x00 0x00 0x3E 0x33 0xA9 0x00 0x00 0x00 0x00 0x00 (write register)  CODEC:  Buf B Biquad A, Right Channel
W 0x00 0x3E (Write PAGE reg)
W 0x48 0x7F 0xFF 0xFF 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 (write register)  CODEC:   Buf B Biquad D, Left Channnel
W 0x00 0x3F (Write PAGE reg)
W 0x50 0x7F 0xFF 0xFF 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 (write register)  CODEC:  Buf B Biquad D,, Right Channel
W 0x00 0x01 (Write PAGE reg)
W 0x14 0x25 (write register)  CODEC:  De-pop
W 0x0C 0x08 0x08 (write register)  CODEC:   LDAC/RDAC to HPL/HPR
W 0x0E 0x08 0x08 (write register)  CODEC:  LDAC/RDAC to LOL/LOR
W 0x09 0x3C (write register)  CODEC:  Power up HPL/HPR and LOL/LOR drivers
W 0x0A 0x3B (write register)  CODEC:  (Dan) Set output common mode
W 0x10 0x00 0x00 (write registter)  CODEC:  Unmute HPL/HPR driver, 0dB Gain
W 0x12 0x00 0x00 (write register)  CODEC:  Unmute LOL/LORR driver, 0dB Gain
W 0x00 0x00 (Write PAGE reg)
W 0x41 0x00 0x00 (write register)  CODEC:  DAC => 0dB
W 0x3F 0xD6 (write register)  CODEC:  Power up LDAC/RDAC
W 0x40 0x00 (write register)  CODEC:  Unmute LDAC/RDACCODEC:  INIT DONE

Reading Codec Page 0:
ADDR  0  1  2  3  4  5  6  7   8  9  A  B  C  D  E  F
0x0_ 00 00 60 00 00 11 07 00  38 00 00 85 83 00 80 02
0x1_ 00 08 85 83 80 01 00 04  00 00 01 00 00 00 01 00
0x2_ 00 00 00 00 44 EE 00 00  00 00 00 00 00 00 00 00
0x3_ 00 00 00 00 18 14 05 08  05 00 00 00 01 01 00 D6
0x4_ 00 00 00 00 6F 38 00 00  00 00 00 EE 10 D8 7E E3
0x5_ 00 C0 00 00 00 00 00 00  7F 00 00 00 00 00 00 00
0x6_ 7F 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00
Done reading page 00

Reading Codec Page 1:
ADDR  0  1  2  3  4  5  6  7   8  9  A  B  C  D  E  F
0x0_ 01 08 F0 00 00 00 00 00  00 3C 3B 10 08 08 08 08
0x1_ 00 00 00 00 25 00 00 00  00 00 00 00 00 00 00 00
0x2_ 00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00
0x3_ 00 00 00 00 28 00 20 88  00 20 00 0C 0C 00 03 F0
0x4_ 00 00 00 00 00 00 00 32  00 00 00 00 00 00 00 00
0x5_ 00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00
0x6_ 00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00
0x7_ 00 00 00 00 00 00 00 00  00 00 00 01 00 00 00 00
Done reading page 1

  • 0 in reply to Carlos17153
    TI__Mastermind 29775 points

    How do you intend to process the recording or playback data? If codec is master mode then it will generate the WCLK and BCLK, but if it's slave mode then host has to provide these clocks. Even if codec is generating the clocks, the host needs these clocks so you have to connect to the host. Most processor does support I2S bus.

  • 0 in reply to pdjuandi
    Prodigy 140 points

    We intend to simply pass the audio through the ADC then directly to the DAC, doing a little filtering/equalization in the codec. 

    Is this a legitimate way to use the codec or does the data HAVE to pass externally to another device via the I2S bus?  In other words, can we establish a data path between the ADC and the DAC WITHIN the codec?

  • 0 in reply to Carlos17153
    Prodigy 140 points

    Our microcontroller is just setting up the codec via the I2C bus (not the I2S) and is not intended to be involved in the audio / data path at all.

  • 0 in reply to Carlos17153
    TI__Mastermind 29775 points

    This device does not support ADC-DAC loopback through register setting.

    So you will need to do it externally.

  • 0 in reply to pdjuandi
    Prodigy 140 points

    That explains our inability to get audio through the codec!

  • 0 in reply to pdjuandi
    Prodigy 140 points

    What is the purpose of page 0 register 29 bit D4?

    Bit D4 indicates it will route ADC output to DAC input, which is what we need to do.

  • 0 in reply to Carlos17153
    TI__Mastermind 29775 points

    I think this is also tied to D5 where the codec is slave mode and you need to provide the wclk and bclk from host.

    Give a try anyway.

  • 0 in reply to pdjuandi
    Prodigy 140 points

    Is there any document anywhere that shows the contents of the "Data Interface" block shown below?  I have been unable to find one anywhere.

  • 0 in reply to Carlos17153
    TI__Mastermind 29775 points

    Data Interface is just the audio interface (Audio Serial Interface) block of the host/controller which basically the process of the different audio format.

    If you want to know more of the interface, here is a video on that.

    https://training.ti.com/audio-serial-interface-formats

    Regards.

  • 0 in reply to pdjuandi
    Prodigy 140 points

    OK, thanks.

    If we drive the BCLK and WCLK lines properly, can we pass audio through the codec as follows?

    Analog input -> ADC -> signal processing -> DAC -> analog line out

  • 0 in reply to Carlos17153
    TI__Mastermind 29775 points

    Ya you should be able to if the host is the master and provides the wclk and bclk to codec.