We are using a dsPIC33 (as Master) to drive a TI AIC 3107 Codec, and are not able to get them to properly get in sync with each other.
About 1/3 of the samples (sometimes more) end up being garbage, and generate copious amounts of loud static.
Analysis of the dsPIC's RAM shows the received "corrupted " CODEC sample values ranging
around 0xFFA4, 0xFE38, 0xFD40 for about 1/3 the samples in an 80 word set of samples.
Enclosed are the initialization sequences we are sending to the
AIC 3107. Could you please look at them and give
us some wise words of advice as to what PLL ratios, etc need
to be re-tweaked in the init sequence, to get the two chips
to play nice with each other.
The dsPIC is acting as Master. It is supplying a 512 KHz clock to BCLK
and using a frame clock (WCLK) of 16 KHz. We are using
it to clock two 16-bit words (left channel, then right channel)
from the AIC3107 to the dsPIC. We have tried using it in both
DSP mode and I2S mode, and both fail in similar ways, as described above.
We are sending the following initialization sequence to the
AIC3107 via the I2C port:
Provide hardware reset, then:
w 30 00 00 Reset to page 0
w 30 01 80 Software reset
w 30 07 00 Set default Fsref = 48 kHz, channels off
w 30 02 44 Set Fsref dividers for ADC/DAC to 16 KHz
(we've also tried other ratios of 0x11, 0x33, 0xAA
with no successful results)
w 30 03 11 Set Q=2,P=1 with PLL disabled
w 30 04 80 Set J=32
w 30 05 00 Set D=0000 (high bits)
w 30 06 00 Set D=0000 (low bits)
w 30 08 00 Set BCLK/WCLK as inputs (AIC 3107 acts as slave)
w 30 09 40 Set into DSP mode, word length = 16 bits
(we've also tried I2S mode, without success)
w 30 0B 01 Set R=1
w 30 66 A5 Set N=5, and use BCLK as PLL clock source
w 30 65 00 Set CODEC_CLKIN to PLL
w 30 03 91 Enable PLL, using Q=2,P=1
. . . Setup ADC and DAC parameters . . .
w 30 07 0A Use Fsref = 48Hz and setup channel to DAC paths
. . . Powerup/un-mute ADCs and DACs . . .
Please advise. Thanks much. ---------------------------------------------------------------
