Hi Team,
Using the PCM5122 with a TDM (3wire) bus and the clock signals BCLK and SCLK are 12.288MHz. (8 x 32bit at 48Khz)
The PLL is disabled at this moment
This works fine with an 8x interpolation settings (register 31 bit I16E = 0)
But with an 8x interpolation is the output signal form not so very good on high frequencies.
Therefore we would activate the 16x interpolation, but this gives a distorted output signal.
What doing we wrong and/or which additional registers we must changing.
Thank you.
-Mark