TAS6584Q1EVM: PVDD Foldback settings under PPC3

Dear support,

If I have understood well, the two sections implement the same function. I don't see significant differences in the two separate windows. Each of them limit the output respect to a digital threshold that is choosen by the operator.

I thought that, when enabled, automatically PVDD foldback function reduce the output in function to PVDD level, in order to limit or avoid signal clip.

In product datasheet SLOSE31A PVDD foldback is presented in theese terms:"If PVDD voltage is less than MPOV, the PVDD sensing circuit will reduce gain to ensure that signals can fit within the available PVDD voltage to avoid clipping"

Is that function present in the chip as described in datasheet or we misandestood something? It's possible to set that function in PCC3 software?

TISL and I also asked if that settings of PVDD foldback thresholds, delay, attak and release are settable at register level. At register level seems to be present only an ENABLE/DISABLE function in "DSP_CTRL2 Register (Address = 0x3A)".

Regards

Giacomo

Hi Giacomo

   Yes, the two function all try to limit the final output. If we are only interested in the PVDD foldback, we could set Threshold to 0dB, and usually set the Voltage Scale value to be -0.5dB to make up for the voltage loss on the inductor and Rdson.

giacomo sammuri said:

Is that function present in the chip as described in datasheet or we misandestood something? It's possible to set that function in PCC3 software?

   The PVDD Foldback in second picture is working in this way. If the device found the output going to be higher than the PVDD voltage, which means clipping will happens, PVDD Foldback function will limit the digital data to make the final output not clipping.

giacomo sammuri said:

TISL and I also asked if that settings of PVDD foldback thresholds, delay, attak and release are settable at register level. At register level seems to be present only an ENABLE/DISABLE function in "DSP_CTRL2 Register (Address = 0x3A)".

   I'm sorry the process flow document for 6584 haven't finished, that document should contain the detailed register settings. For now, please use I2C Log function to get the register settings.

Hi Shadow He, 

Thank you for the replay.

Ok, clarified that PVDD foldback is implemented in that way, we have to understand where is our set-up mistake.

We made a very simple setup to verify PVDD Foldback function (because during some different tests we noted some clip event during supply foldback).

1) We put in input of the TAS6485EVAL a sine wave at 1kHz. PVDD supply voltage starting value was 20V. 

2) We encreased the output voltage amplitute so that the sine peak value was 15V.

3) At that point we started to lower output voltage down to 15V and beyond.

We expected to see an attuenation on the output when pvdd became lower than 15V, in order to avoid clipping. This didn't happen. I attach here the setting window capures and also the scope captures of the clipping.

Do you have any idea on the reason way we can't see PVDD foldback in action?

Regards

Giacomo

Hi Shadow He,

Sorry for the delay in the answer.

Ok, now I can successfully activate PVDD foldback function. 

I repeated the same test shown in the preview post. We saw that, activating PVDD foldback during clipping, the out signal was scaled in order to eliminate the distortion. Varying the PVDD supply the out-signal followed proportionally, with the same factor of attenuation, the rails variation.

Anyway, if the volume is increased, we are able to make the output clip again to the rail voltage.

I didn't expect that. I expect that PVDD foldback function dynamically adjust output signal in function also of the volume, in order to avoid PVDD clipping in every condition of gain and volume. 

It sounds like that PVDD foldback attenuate the output signal of a preset quantity respect to the Voltage Rail level based on the initial volume setting.

Is that behavior correct? It’s correct that if the user changes the volume beyond a certain threshold the signal in the output can clip to the rails?

Furthermore, the attenuation seems not connected to the effective THD produced by the out signal. In fact, applying a different % quantity of THD in the menu, the attenuation factor is the same for all the levels.

Ok. Following the new istructions we managed the PVDD foldback. 

The PCC3 seem to have still some bugs, because sometime this procedure fail and you have to reset the board. Anyway thank you very much for the support.