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TLV320AIC3204: The line output drivers do not get powered up

Part Number: TLV320AIC3204


 I am trying to initialize the codec to only output for now. Trying to use the line out's, but the line out drivers never power up.

My code initializes the codec as outlined in section 2.4.6 of the reference manual. P0R37 shows the flags for both DAC's are powered up after initialization, but the line output drivers are not (therefore I get no output from the codec). I have been struggling for a while on this, can someone help me out.

Initialization code:

AIC_writeRegister(AIC3106_REG_PAGESELECT, 0);
    AIC_writeRegister(AIC3106_REG_RESET, 1);
    /* Configure AIC3204 */
    //###############################################
    //# Clock and Interface Settings
    AIC_writeRegister(AIC3106_REG_PAGESELECT, 0);
    AIC_writeRegister(11,0b10000001);//Power up the NDAC divider with value 1
    AIC_writeRegister(12,0b10000100);//Power up the MDAC divider with value 4
    AIC_writeRegister(18,0b10000001);//Power up the NADC divider with value 1
    AIC_writeRegister(19,0b10000100);//Power up the MADC divider with value 4
    AIC_writeRegister(14,32);// Program the DOSR to 32 for 192ksps
    AIC_writeRegister(20,32);// Program the AOSR to 32 for 192ksps
    AIC_writeRegister(27,1);//I2s and 16 bit | CHANGE TO DSP AND 32 BIT EVENTUALY  (DOUT is high impedance while not used)
    AIC_writeRegister(28, 0x00);// Data offset = 0
    AIC_writeRegister(60,17);//Set the DAC processing block to PRB_P17
    AIC_writeRegister(61,13);//Set the ADC processing block to PRB_P13
    //###############################################


    //###############################################
    //# Program Analog Blocks
    AIC_writeRegister(AIC3106_REG_PAGESELECT, 1);//Select Page 1
    AIC_writeRegister(1, 8);// Disable crude AVDD generation from DVDD
    AIC_writeRegister(2, 1);// Enable Analog Blocks, use LDO power
    AIC_writeRegister(10, 0b00111011);//Program Common Mode voltage default is 0.9v
    AIC_writeRegister(123, 1);//Reference charges up in 40ms after analog blocks
    AIC_writeRegister(14,0b00001000);//rout lol
    AIC_writeRegister(15,0b00001000);//rout lor
    AIC_writeRegister(18,0);//lol unmute ,0b00011011 for 27 db
    AIC_writeRegister(19,0);//lor unmute
    AIC_writeRegister(9,0x00001100);//Power up loL and loR drivers

    //###############################################


     //###############################################
     //# Power Up DAC
     AIC_writeRegister(AIC3106_REG_PAGESELECT, 0);//Select Page 0
     AIC_writeRegister( 64, 2 ); // Left vol=right vol &unmute
     AIC_writeRegister(63,0b11010100);//Power up LDAC/RDAC (soft-step one per DAC word)
     AIC_writeRegister(64,0);//Unmute LDAC/RDAC
     //###############################################

Michael

  • Hi Michael,

    Are you not seeing an output on both the right and left channel DAC, both LOR/LOL?

    Do you see an output on HPR/HPL? I would confirm the DAC channels are not routed to headphone outputs in register 12/13, page 1. Making sure D3 is 0.

    Regards,

  • No output at either LOL or LOR (the I2S stream known good). They go to 1.5 volts at the line "AIC_writeRegister(10, 0b00111011);//Program Common Mode voltage default is 0.9v". I'm not trying to use HPR/L and their output is zero volts.

    These are the registers I read after initialization for debugging.

    value of register p0-36: 0
    value of register p0-37:136   (0b 1000 1000)
    value of register p0-38: 0
    value of register p1-12: 0
    value of register p1-13: 0

    p0 R37 Should really be 0b 1100 1100, but I never get this.

  • Hi Michael,

    If the device was resetting the DAC would power down as well. It seems LOL/LOR are powering down even after power up initialization in pg 1, 0x09. This could be a hardware issue, remove the load if any on the line outs and check for signal using scope.

    Are you configuring the device in stereo single ended or mono differential?

    If mono differential, LOR/LOL need to be powered by AVDD not LDOIN shown in page0, R10

    Regards,

  • Thanks for your help Deveon, but everything I have tried so far does not flip the P0_R37 (D6 or D2) to 1. I can't get the line out drivers to power up.

    You said the line out drivers could be powering down while I'm initializing them, so tried power cycling the codec and initializing it without the soft reset at the beginning, no dice.

    I removed the load from line outs and probed them. If P1_R10 D3=1 line out is AVdd, If P1_R10 D3=0 line out is 0V. (I have tried the on chip LDO regulator for generation of AVdd and Dvdd, as well as generating them externally. no difference)

    I'm trying to do stereo single ended outputs from LOL and LOR.

    Code Output:

    ---------------------------------------------------

    value of register p0-37: 0
    value of register p0-36: 0
    value of register p0-37:136
    value of register p0-38: 0
    value of register p1-9: 0
    value of register p1-12: 0
    value of register p1-13: 0

     //Clock source =master clock in = 24.576MHz, DAC sampling freq =192Ksps
        AIC_writeRegister(AIC3106_REG_PAGESELECT, 0);
        AIC_writeRegister(AIC3106_REG_RESET, 1);
    
        uint8_t value;int i;
        //TEST DAC flag REGISTERs
        AIC_writeRegister(AIC3106_REG_PAGESELECT, 0);
        AIC_readRegister(37,&value);
        UART_txString(DEBUG_PORT, "value of register p0-37:");
        UART_txUint8(DEBUG_PORT,value);
        UART_txString(DEBUG_PORT, "\r\n");
    
    
        //###############################################
        //# Clock and Interface Settings
        AIC_writeRegister(AIC3106_REG_PAGESELECT, 0);
        AIC_writeRegister(11,0b10000001);//Power up the NDAC divider with value 1
        AIC_writeRegister(12,0b10000100);//Power up the MDAC divider with value 4
        AIC_writeRegister(18,0b10000001);//Power up the NADC divider with value 1
        AIC_writeRegister(19,0b10000100);//Power up the MADC divider with value 4
        AIC_writeRegister(14,32);// Program the DOSR to 32 for 192ksps
        AIC_writeRegister(20,32);// Program the AOSR to 32 for 192ksps
        AIC_writeRegister(27,1);//I2s and 16 bit | CHANGE TO DSP AND 32 BIT EVENTUALY  (DOUT is high impedance while not used)
        AIC_writeRegister(28, 0x00);// Data offset = 0
        AIC_writeRegister(60,17);//Set the DAC processing block to PRB_P17
        AIC_writeRegister(61,13);//Set the ADC processing block to PRB_P13
        //###############################################
    
        //At this point, at the latest, the analog power supply must be applied to the device
    
        //###############################################
        //# Program Analog Blocks
        AIC_writeRegister(AIC3106_REG_PAGESELECT, 1);//Select Page 1
        AIC_writeRegister(1, 8);// Disable crude AVDD generation from DVDD
        AIC_writeRegister(2, 1);// Enable Analog Blocks, use LDO power
        AIC_writeRegister(10, 0b00000011);//Program Common Mode voltage default is 0.9v  HERE 1.5v
        AIC_writeRegister(123, 1);//Reference charges up in 40ms after analog blocks
        AIC_writeRegister(14,0b00001000);//rout lol
        AIC_writeRegister(15,0b00001000);//rout lor
        AIC_writeRegister(18,0);//lol unmute ,0b00011011 for 27 db
        AIC_writeRegister(19,0);//lor unmute
        AIC_writeRegister(9,0x00001100);//Power up loL and loR drivers
        //###############################################
    
    
    
         //###############################################
         //# Power Up DAC
         AIC_writeRegister(AIC3106_REG_PAGESELECT, 0);//Select Page 0
         AIC_writeRegister( 64, 2 ); // Left vol=right vol &unmute
         AIC_writeRegister(63,0b11010100);//Power up LDAC/RDAC (soft-step one per DAC word)
         AIC_writeRegister(64,0);//Unmute LDAC/RDAC
         //###############################################
    
    
         //TEST flag REGISTERs
         AIC_writeRegister(AIC3106_REG_PAGESELECT, 0);
         AIC_readRegister(36,&value);
         UART_txString(DEBUG_PORT, "value of register p0-36:");
         UART_txUint8(DEBUG_PORT,value);
         UART_txString(DEBUG_PORT, "\r\n");
         AIC_readRegister(37,&value);
         UART_txString(DEBUG_PORT, "value of register p0-37:");
         UART_txUint8(DEBUG_PORT,value);
         UART_txString(DEBUG_PORT, "\r\n");
         AIC_readRegister(38,&value);
         UART_txString(DEBUG_PORT, "value of register p0-38:");
         UART_txUint8(DEBUG_PORT,value);
         UART_txString(DEBUG_PORT, "\r\n");
         AIC_writeRegister(AIC3106_REG_PAGESELECT, 1);
         AIC_readRegister(9,&value);
         UART_txString(DEBUG_PORT, "value of register p1-9:");
         UART_txUint8(DEBUG_PORT,value);
         UART_txString(DEBUG_PORT, "\r\n");
         AIC_readRegister(12,&value);
         UART_txString(DEBUG_PORT, "value of register p1-12:");
         UART_txUint8(DEBUG_PORT,value);
         UART_txString(DEBUG_PORT, "\r\n");
         AIC_readRegister(13,&value);
         UART_txString(DEBUG_PORT, "value of register p1-13:");
         UART_txUint8(DEBUG_PORT,value);
         UART_txString(DEBUG_PORT, "\r\n");

  • Hi Michael,

    Daveon is out of the office today. He should be in the office tomorrow to look further into this. thank you for your patience. 

    Regards,
    Arthur

  • Hi Michael,

     Audio expert tested similar scenario a couple months ago. Please try changing the value of Page 1 R9 to 0x0C and keeping Page 1 R10 at 0x08 should be fine.

    For your reference: https://e2e.ti.com/support/audio-group/audio/f/audio-forum/1135799/tlv320aic3204-setting-lol-lor-power-down-won-t-take-affect-when-line-output-is-configured-powered-by-ldoin

    Additional: https://e2e.ti.com/support/audio-group/audio/f/audio-forum/979248/tlv320aic3204-line-out-routing