PCM4220

Ignacio Linares

Other Parts Discussed in Thread: PCM4220

My customer has the following questions:

I will be using two chips as a slaves to a master clock source generated by a FPGA. I want to know how internal sampling is synchronized to the external source? I see two possibilities 1) The LRCLK only defines left / right channel data on the serial output port and the /RST pin aligns the digital filter or 2) The LRCLK aligns the internal digital filter. I want to be sure that new samples output from the internal digital filter of both chips happen at the same time.

over 14 years ago

0 Don Dapkus over 14 years ago

TI__Guru**** 189401 points

Hi, Ignacio,

Let me look into this for you.

-d2

0 Don Dapkus over 14 years ago in reply to Don Dapkus

TI__Guru**** 189401 points

Hi, Ignacio,

Sorry for the delay. I am still working on this for you.

-d2

0 Don Dapkus over 14 years ago in reply to Don Dapkus

TI__Guru**** 189401 points

Hi, Ignacio,

I have run into a dead end here. In order for me to continue, I will have to expend a lot more effort. Is this information still needed by your customer, or is the issue already closed?

-d2

0 Ignacio Linares over 14 years ago in reply to Don Dapkus

Expert 1655 points

I just checked with my customer, and they do need to understand this. Here is what he said:

We are going to be running two chips in the board we are having the layout done for right now. A possible future board will have three chips.

We DO want to make sure that multiple chips are time aligned. We want to align the center of a sample to a GPS time reference.

So my original question still stands and is unanswered.

1) Does the PCM4220 Reset align the digital filter and define the center of a sample or

2) Does the LRCLK somehow align the digital filter and define the center of a sample.

0 Don Dapkus over 14 years ago in reply to Ignacio Linares

TI__Guru**** 189401 points

Ignacio,

OK, forge ahead I will.

-d2

0 Don Dapkus over 14 years ago in reply to Don Dapkus

TI__Guru**** 189401 points

Ignacio,

OK, here's what I found:

For the three chips configuration, I believe that the slave mod is the only choice. The reset pin controls the hardware filter’s reset, and when release the reset pin the on chip state machines of the different chip should work identically. So, the output data should be aligned.

-d2

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