• State Resolved
  • Locked Locked
  • Replies 3 replies
  • Subscribers 30 subscribers
  • Views 1455 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TLV320AIC3109-Q1: Supported Audio Data Word Length and I2S Slot Width

Gabriel Lin
Prodigy 20 points
Part Number: TLV320AIC3109-Q1

Hi,

I'm working with TLV320AIC3109-Q1 on our custom board and we would like to transmit the audio data in I2S mode. In the register description and I2S mode description in section 7.3.2.3, we only find the valid data length configuration but not the slot width configuration. Would like to ask if the the combinations of the slot-width and valid data length are as the following:

Page 0, Reg 9, Bit 4-5

0x00 data word length = 16 bits ==> is slot-width 16 bits too?
0x01 data word length = 20 bits ==> is slot-width 20 bits too?
0x10 data word length = 24 bits ==> is slot-width 32 bits? (As the format S24_LE in the Linux Kernel)
0x11 data word length = 32 bits ==> is slot-width 32 bits too?

Thanks,
Gabriel

  • 0
    TI__Mastermind 27330 points

    Hi,

    I may not be fully understanding your question. In register 9 user can program the word length to be up to 32-bit length meaning the max amount of data bits is 32. Both left and right channel of I2S mode will be 32-bit length and user can have the data length be less than word length with unused data bits or offset data bits.

    Regards,

  • 0
    Prodigy 20 points

    Hi Daveon,

    Based on the reply, do you mean that the combinations of valid data length and slot width are not limited to what I mentioned as long as the slot-width is longer than data word length, there will be no problem, is that correct?

    Assuming that we config the data word length to 24-bit while the i2s bit clock is generated based on 32-bit slot width, are those unused 8-bit(from LSB + 7 to LSB) padded with 0 when the AIC3109 sends data? Vice versa, does AIC3109 expect the unused 8-bit(from LSB + 7 to LSB) be padded with 0?

    Thanks,
    Gabriel

  • +1 in reply to Gabriel Lin
    TI__Mastermind 27330 points

    Hi Gabriel,

    Correct, the remaining unused data-bits will be 0 in from LSB+7-LSB in LJ mode. The order of bits is determined by which mode as well.

    Regards,