PCM1840EVM: Audio Noise

Marvn Arcangel

Part Number: PCM1840EVM
Other Parts Discussed in Thread: REG1117, PCM1840,

Hi Team,

Can you please help with the issue below?

A PCM1480EVM connected to DE10Standard which generates all digital clocks (BCLK, FSYNC and MCLK)
MCLK = 12MHz, see page 1
BCLK = 3.072289MHz, see page 1
FSYCK = 64*BCLK =48KHz, see page 2

The power source is a benchtop DC power supply model # CPS-3010 II feeding 5.15 VDC (see page 3) through a REG1117 regulator.

The audio captured is very noisy. The test result on page 4 shows a DFT of the PCM1480EVM i2s audio output where a tone of 4437Hz is played through a phone speaker to the onboard microphone. The pointer shows the tone of the speaker.
What is the source of the noise other than the input 4343HZ tone on page 4 of the attachment?

Please let me know if you need more information.

Thanks in advance.

Regards,

Marvin

over 2 years ago

0 Sanjay Dixit over 2 years ago

TI__Mastermind 23030 points

shall reply in a few hours

0 Marvn Arcangel over 2 years ago in reply to Sanjay Dixit

TI__Genius 10940 points

Hi Sanjay,

Thank you. I will wait for your response.

Regards,

Marvin

0 Sanjay Dixit over 2 years ago in reply to Marvn Arcangel

TI__Mastermind 23030 points

MCLK amplitude looks very small.Why is this so?

0 Marvn Arcangel over 2 years ago in reply to Sanjay Dixit

TI__Genius 10940 points

Hi Sanjay,

Thank you for waiting. The fpga output is 2.2 vpp for MCLK despite sharing the same bank and settings as other signals.

I hope this information helps. Let me know if you need more.

regards,

Marvin

0 Sanjay Dixit over 2 years ago in reply to Marvn Arcangel

TI__Mastermind 23030 points

Shall respond on Tuesday

0 Marvn Arcangel over 2 years ago in reply to Sanjay Dixit

TI__Genius 10940 points

Hi Sanjay,

Looking forward to your response.

Regards,

Marvin

0 Daveon Douglas over 2 years ago in reply to Marvn Arcangel

TI__Mastermind 20880 points

HI Marvin, TI experts were out of office yesterday, you should expect a response from sanjay today

0 Sanjay Dixit over 2 years ago in reply to Daveon Douglas

TI__Mastermind 23030 points

Are you sure you are using PCM1840? It does not have a MCLK pin. Where are you connecting MCLK.

Also if the Timings are generated from a Common source it needs to be a multiple of 48Khz. The MCLK should be 12.288 Mhz

Can you please also send me the Hardware pin settings you use?

0 Marvn Arcangel over 2 years ago in reply to Sanjay Dixit

TI__Genius 10940 points

Hi Sanjay,

The MCLK is connected to MD1.

MCLK = 12 MHz. MD0 is low. This makes fs = 46.875 which is the LRCLK frequency. All clocks are generated by the FPGA. The customer need to expand to a microphone array in the future. Hence they cant use the internal clocks.

Regards,

Marvin

0 Daveon Douglas over 2 years ago in reply to Marvn Arcangel

TI__Mastermind 20880 points

Hi Marvin,

Out TI expert Sanjay is out of office so please be patient as another expert will address question next week.

Thank you for your patience

0 Marvn Arcangel over 2 years ago in reply to Daveon Douglas

TI__Genius 10940 points

Hi Daveon,

Thank you. I am looking forward to their response.

Regards,

Marvin

0 Daveon Douglas over 2 years ago in reply to Marvn Arcangel

TI__Mastermind 20880 points

Hi Marvin,

Apologies for the delay, our TI expert, Jeff, will respond your question as soon as possible.

Thanks,

0 Marvn Arcangel over 2 years ago in reply to Daveon Douglas

TI__Genius 10940 points

Hi Daveon,

Looking forward to this. Thank you very much.

0 Jeff Julich over 2 years ago in reply to Marvn Arcangel

TI__Intellectual 2030 points

Hi Marvin,

I am not understanding the MCLK connection. In the diagram you have "12 MHz" on MD0 while you state the MCLK is on MD1. The MCLK in this config with Fs=48kHz should be exactly 12.288MHz. From the diagram, the MCLK looks floating off gnd and small signal. I don't know if the part will recognize it.

0 Marvn Arcangel over 2 years ago in reply to Jeff Julich

TI__Genius 10940 points

Hi Jeff

The customer is feeding MCLK through the pin labeled "MCLK" in the EVM. This feeds to MD1 according to page 12 of the PCM1840EVM datasheet:

The customer will measure the exact MCLK frequency and will update us with the exactly but it is above 12MHz +5% according to them. they didn't think it matters because all other clocks are synched to MCLK.

MCLK is not floating and the floating waveform is due to the default settings of their USB oscilloscope.

They assume the sampling circuit recognizes MCLK because of the dout digital stream that they get. but never get dout data stream if any of the clocks is not within acceptable ranges.

0 Jeff Julich over 2 years ago in reply to Marvn Arcangel

TI__Intellectual 2030 points

Hi Marvin,

Please confirm that the signal integrity is good on MCLK. This could definitely be the issue if not.

Please confirm that MDZ is high. Please let me know setting of FMT0, FMT1, and MD0 as well.

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PCM1840EVM: Audio Noise