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TLV320ADC5140: Unable to powerup the input channels DEV_STS0 and DEV_STS1 indicate channels are not powered up.

Part Number: TLV320ADC5140

Hi I am configuring the TLV320ADC5140 via I2C and I cannot get the input channels powered up. 

I am configruing IN1P and IN2P as two inputs to ADC as line input and signle ended.

I am providing the script I am using to configure, can you please help me find the missing config? 

def rawConfigTLVADC(addr):
    TLVADC5140 = TLVADC5140Slave(addr)
    SLEEP_CFG = 0x02

    ASI_CFG0 = 0x07
    ASI_CFG1 = 0x08
    MST_CFG0 = 0x13
    MST_CFG1 = 0x14
    # ASI_STS  = 0x15
    GPIO_CFG0 = 0x21
    GPI_CFG0  = 0x2B
    GPI_CFG1  = 0x2C

    CH1_CFG0  = 0x3C
    CH2_CFG0  = 0x41

    IN_CH_EN = 0x73
    ASI_OUT_CH_EN = 0x74
    PWR_CFG = 0x75

    TLVADC5140.WritetoTLVADC5140([SLEEP_CFG], 0x81)
    sleep(0.001) # 1mS

   
    TLVADC5140.WritetoTLVADC5140([ASI_CFG0], 0x60) # I2S , 24 bit format
    sleep(0.002) # 2mS
   
    TLVADC5140.WritetoTLVADC5140([ASI_CFG1], 0x20)
    sleep(0.002) # 2mS
   
    TLVADC5140.WritetoTLVADC5140([GPIO_CFG0], 0xA0)
    sleep(0.002) # 2mS
   
    TLVADC5140.WritetoTLVADC5140([GPI_CFG0], 0x00)
    sleep(0.002) # 2mS
    TLVADC5140.WritetoTLVADC5140([CH1_CFG0], 0xA0)
    sleep(0.002) # 2mS
    TLVADC5140.WritetoTLVADC5140([CH2_CFG0], 0xA0)
    sleep(0.002) # 2mS

    TLVADC5140.WritetoTLVADC5140([IN_CH_EN], 0xC0)
    sleep(0.002) # 2mS
    TLVADC5140.WritetoTLVADC5140([ASI_OUT_CH_EN], 0xC0)
    sleep(0.002) # 2mS
    TLVADC5140.WritetoTLVADC5140([PWR_CFG], 0xE0)
    sleep(0.002) # 2mS

    data1 = TLVADC5140.ReadFromTLVADC5140([0x76])
    print("DEV_STS0 = 0x{0:02X} - CH STATUS 0-powered down 1-powered up ".format(data1))

    data1 = TLVADC5140.ReadFromTLVADC5140([0x77])
    print("DEV_STS1 = 0x{0:02X} - MODE STATUS 0x80 - Sleep mode 0xC0- Active mode channels OFF 0xE0 - Active mode channels ON ".format(data1))
  • Hi,

    I'm out of office today for US holiday, please be patient as responses are delayed.

  • Hi Can I get response today as this is really urgent to solve.

  • # CHECKSUM 0
    # Generated by ADCx140EVM-SW v3.0.5
    # TLV320ADC5140 device configuration
    # -----------------------------------------------------------------------------
    # Reset
    # -----------------------------------------------------------------------------
    # Select Page 0
    w 98 00 00
    # Reset Device
    w 98 01 01
    # 1mS Delay
    # -----------------------------------------------------------------------------
    # Begin Device Memory
    # -----------------------------------------------------------------------------
    # Page 0 (0x00) Dump
    # Select Page 0
    w 98 00 00
    # Wake up and enable AREG
    w 98 02 81
    w 98 05 05
    # ASI Configuration
    w 98 07 30
    w 98 08 00
    w 98 09 00
    # ASI Channel Configuration
    w 98 0b 00
    w 98 0c 01
    w 98 0d 02
    w 98 0e 03
    w 98 0f 04
    w 98 10 05
    w 98 11 06
    w 98 12 07
    # Master mode configuration
    w 98 13 02
    w 98 14 48
    # Clock Configuration
    w 98 16 10
    # PDM Configuration
    w 98 1f 40
    w 98 20 00
    # GPIO Configuration
    w 98 21 22
    # GPO Configuration
    w 98 22 00
    w 98 23 00
    w 98 24 00
    w 98 25 00
    w 98 29 00
    # GPI Configuration
    w 98 2b 00
    w 98 2c 00
    w 98 32 00
    w 98 33 ff
    w 98 3b 60
    # Channel 1 configuration
    w 98 3c a1
    w 98 3d 00
    w 98 3e c9
    w 98 3f 80
    w 98 40 00
    # Channel 2 configuration
    w 98 41 a1
    w 98 42 00
    w 98 43 c9
    w 98 44 80
    w 98 45 00
    # Channel 3 configuration
    w 98 46 a1
    w 98 47 00
    w 98 48 c9
    w 98 49 80
    w 98 4a 00
    # Channel 4 configuration
    w 98 4b a1
    w 98 4c 00
    w 98 4d c9
    w 98 4e 80
    w 98 4f 00
    # Channel 5 configuration
    w 98 52 c9
    w 98 53 80
    w 98 54 00
    # Channel 6 configuration
    w 98 57 c9
    w 98 58 80
    w 98 59 00
    # Channel 7 configuration
    w 98 5c c9
    w 98 5d 80
    w 98 5e 00
    # Channel 8 configuration
    w 98 61 c9
    w 98 62 80
    w 98 63 00
    #DSP configuration
    w 98 6b 01
    w 98 6c 40
    # DRE configuration
    w 98 6d 7b
    # AGC configuration
    w 98 70 e7
    # Channel Input/Output Configuration
    w 98 73 f0
    w 98 74 f0
    # Page 2 (0x02) Dump
    # Select page 2
    w 98 00 02
    # Biquad 1 coefficients (N0, N1, N2, D1, D2)
    w 98 08 7f
    > ff
    > ff
    > ff
    w 98 0c 00
    > 00
    > 00
    > 00
    w 98 10 00
    > 00
    > 00
    > 00
    w 98 14 00
    > 00
    > 00
    > 00
    w 98 18 00
    > 00
    > 00
    > 00
    # Biquad 2 coefficients
    w 98 1c 7f
    > ff
    > ff
    > ff
    w 98 20 00
    > 00
    > 00
    > 00
    w 98 24 00
    > 00
    > 00
    > 00
    w 98 28 00
    > 00
    > 00
    > 00
    w 98 2c 00
    > 00
    > 00
    > 00
    # Biquad 3 coefficients
    w 98 30 7f
    > ff
    > ff
    > ff
    w 98 34 00
    > 00
    > 00
    > 00
    w 98 38 00
    > 00
    > 00
    > 00
    w 98 3c 00
    > 00
    > 00
    > 00
    w 98 40 00
    > 00
    > 00
    > 00
    # Biquad 4 coefficients
    w 98 44 7f
    > ff
    > ff
    > ff
    w 98 48 00
    > 00
    > 00
    > 00
    w 98 4c 00
    > 00
    > 00
    > 00
    w 98 50 00
    > 00
    > 00
    > 00
    w 98 54 00
    > 00
    > 00
    > 00
    # Biquad 5 coefficients
    w 98 58 7f
    > ff
    > ff
    > ff
    w 98 5c 00
    > 00
    > 00
    > 00
    w 98 60 00
    > 00
    > 00
    > 00
    w 98 64 00
    > 00
    > 00
    > 00
    w 98 68 00
    > 00
    > 00
    > 00
    # Biquad 6 coefficients
    w 98 6c 7f
    > ff
    > ff
    > ff
    w 98 70 00
    > 00
    > 00
    > 00
    w 98 74 00
    > 00
    > 00
    > 00
    w 98 78 00
    > 00
    > 00
    > 00
    w 98 7c 00
    > 00
    > 00
    > 00
    # Page 3 (0x03) Dump
    # Select page 3
    w 98 00 03
    # Biquad 7 coefficients
    w 98 08 7f
    > ff
    > ff
    > ff
    w 98 0c 00
    > 00
    > 00
    > 00
    w 98 10 00
    > 00
    > 00
    > 00
    w 98 14 00
    > 00
    > 00
    > 00
    w 98 18 00
    > 00
    > 00
    > 00
    # Biquad 8 coefficients
    w 98 1c 7f
    > ff
    > ff
    > ff
    w 98 20 00
    > 00
    > 00
    > 00
    w 98 24 00
    > 00
    > 00
    > 00
    w 98 28 00
    > 00
    > 00
    > 00
    w 98 2c 00
    > 00
    > 00
    > 00
    # Biquad 9 coefficients
    w 98 30 7f
    > ff
    > ff
    > ff
    w 98 34 00
    > 00
    > 00
    > 00
    w 98 38 00
    > 00
    > 00
    > 00
    w 98 3c 00
    > 00
    > 00
    > 00
    w 98 40 00
    > 00
    > 00
    > 00
    # Biquad 10 coefficients
    w 98 44 7f
    > ff
    > ff
    > ff
    w 98 48 00
    > 00
    > 00
    > 00
    w 98 4c 00
    > 00
    > 00
    > 00
    w 98 50 00
    > 00
    > 00
    > 00
    w 98 54 00
    > 00
    > 00
    > 00
    # Biquad 11 coefficients
    w 98 58 7f
    > ff
    > ff
    > ff
    w 98 5c 00
    > 00
    > 00
    > 00
    w 98 60 00
    > 00
    > 00
    > 00
    w 98 64 00
    > 00
    > 00
    > 00
    w 98 68 00
    > 00
    > 00
    > 00
    # Biquad 12 coefficients
    w 98 6c 7f
    > ff
    > ff
    > ff
    w 98 70 00
    > 00
    > 00
    > 00
    w 98 74 00
    > 00
    > 00
    > 00
    w 98 78 00
    > 00
    > 00
    > 00
    w 98 7c 00
    > 00
    > 00
    > 00
    # Page 4 (0x04) Dump
    # Select page 4
    w 98 00 04
    w 98 08 7f
    > ff
    > ff
    > ff
    w 98 0c 00
    > 00
    > 00
    > 00
    w 98 10 00
    > 00
    > 00
    > 00
    w 98 14 00
    > 00
    > 00
    > 00
    w 98 18 00
    > 00
    > 00
    > 00
    w 98 1c 7f
    > ff
    > ff
    > ff
    w 98 20 00
    > 00
    > 00
    > 00
    w 98 24 00
    > 00
    > 00
    > 00
    w 98 28 00
    > 00
    > 00
    > 00
    w 98 2c 00
    > 00
    > 00
    > 00
    w 98 30 7f
    > ff
    > ff
    > ff
    w 98 34 00
    > 00
    > 00
    > 00
    w 98 38 00
    > 00
    > 00
    > 00
    w 98 3c 00
    > 00
    > 00
    > 00
    w 98 40 00
    > 00
    > 00
    > 00
    w 98 44 7f
    > ff
    > ff
    > ff
    # High pass filter coefficients
    w 98 48 7f
    > ff
    > ff
    > ff
    w 98 4c 00
    > 00
    > 00
    > 00
    w 98 50 00
    > 00
    > 00
    > 00
    w 98 54 00
    > 00
    > 00
    > 00
    # Power up/down
    # Select page 0
    w 98 00 00
    w 98 75 00
    
    
    
    

    Attached is single-ended configuration preset code for ADC5140, try this and see if it works.

    I also recommend downloading PPC3 the GUI for ADC5140 for characterization and register dump

  • Hi thank you for attaching the preset code. I have couple of questions

    1) I see most of them are at reset value so I assume I do not need to write them again. Especially with Coefficient and DSP regs as I do not use them. 

    2) The other questions I had with PWR_CFG 0x75 register, in the above code it is set to 0x00, at what state I need to power them up? 

    3) I need to use only two inpur channels so I do not need to configure channels 3 to 8 , am I right? 

  • Hi Uma,

    Yes, the register dump I attached before included default values. Attached is all that is needed to write to device:

     

    # CHECKSUM 0
    # Generated by ADCx140EVM-SW v3.0.5
    # TLV320ADC5140 device configuration
    # -----------------------------------------------------------------------------
    # Reset
    # -----------------------------------------------------------------------------
    # Select Page 0
    w 98 00 00
    # Reset Device
    w 98 01 01
    # 1mS Delay
    # -----------------------------------------------------------------------------
    # Begin Device Memory
    # -----------------------------------------------------------------------------
    # Page 0 (0x00) Dump
    # Select Page 0
    w 98 00 00
    # Wake up and enable AREG
    w 98 02 81
    # GPI Configuration
    w 98 3b 60
    # Channel 1 configuration
    w 98 3c a1
    # Channel 2 configuration
    w 98 41 a1
    # Channel 3 configuration
    w 98 46 a1
    # Channel 4 configuration
    w 98 4b a1
    # Channel Input/Output Configuration
    w 98 73 c0
    w 98 74 f0
    # Power up/down
    # Select page 0
    w 98 00 00
    w 98 75 60
    

    In code the  ACTIVE MODE is set after all registers are configured by [w 98 75 60]. Also, SDOUT has two data slot "channels" for left + right data of I2S for each input that is enabled whether differential or single-ended input. Channels 5:8 can remain in default configuration since IN3x & IN4x are disabled