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PCM1840: PCM1840: Power-up, reset and power down behaviour. Are these sequences are okay?

Michi S
Intellectual 265 points
Part Number: PCM1840

Hello,

we designed in the PCM1840 on a board. There are 5 ADCs, 1 x as master and 4 x as slave. After a few adjustments, these work well and the processing in the FPGA also works very well.

Our question now is whether the following sequences are okay or whether adjustments are still necessary for stable operation.

Info: AVDD = IOVDD with the same voltage level 3,3 V

1. PowerUp behaviour:

Information from the data sheet: Shdnz must still be kept 100 us low after the 3.3 V supply is stable.

But at what voltage level the 3.3 V considered as stable?

2. Reset during normal operation (AVDD and IOVDD are stable with 3,3 V voltage level):

We did not found a minimum time for an active reset (shdnz = low) in the datasheet. Is this time sufficient to reset the ADC or what is the minimum time on shdnz to reset the ADCs?

3. PowerDown:

If the power supply run down, we can't pull the shutdown pin (SHDNZ) low (shutdown is active) 10 ms or any time before AVDD and IOVDD run down under the minimum recommended voltage of 3.0 V.

When this voltage drops, the ADC data is no longer processed. This means that it does not matter what the ADC delivers on its data lines.

After this sequence it starts later like in point "1. PowerUp behaviour"

Is this behaviour okay?

Our question now is are thease sequences 1 , 2 and 3 are okay or whether adjustments are still necessary for stable operation in the field by our customers?

We look forward to your feedback with more information.

Thank you and best regard,

  • 0
    TI__Mastermind 23030 points

    Some Answers:

    1.ut at what voltage level the 3.3 V considered as stable?

    Ans: The Operating Voltage is the Stable Level. For 3.3v IOVDD the Stable Level is 3.3v

    2. We did not found a minimum time for an active reset (shdnz = low) in the datasheet. Is this time sufficient to reset the ADC or what is the minimum time on shdnz to reset the ADCs?

    Ans: 

    Please refer to Page 26. A minimum time of 25 ms is needed to enter into shutdown. Your time seems much shorter. 

    3.f the power supply run down, we can't pull the shutdown pin (SHDNZ) low (shutdown is active) 10 ms or any time before AVDD and IOVDD run down under the minimum recommended voltage of 3.0 V.

    When this voltage drops, the ADC data is no longer processed. This means that it does not matter what the ADC delivers on its data lines.

    After this sequence it starts later like in point "1. PowerUp behaviour"

    Ans: Please refer to figure below. Device goes into Shutdown once AVDD is reoved, The Moment Avdd goes to zero device is Shutdown,

    This sequence will work.

    Ans

  • 0 in reply to Sanjay Dixit
    Intellectual 265 points

    We have a few more questions about our question 2 and your answer.

    We do not need a shutdown in our application to fade out or save power, but "only" to reset the ADCs if they are in a possible error state.
    - Is it possible for the ADCs to get into an error state?
    - Is it just a shutdown or a real reset for the ADCs?
    - In which cases should the SHDNZ be used, except for fading out?
    - Is our "short" time on the shutdown signal SHDNZ sufficient for reset the ADC (we don't need fade out and with our smaller SHDNZ signal we can see the fade out later on the data from the ADC) or does it have to be at least 25 ms long to reset the ADC?

  • 0 in reply to Michi S
    TI__Mastermind 23030 points

    I shall revert in a few hours.

  • 0 in reply to Sanjay Dixit
    TI__Mastermind 23030 points

    Selection from Datasheet:

    If the SHDNZ pin is asserted low when the device is in active mode, the device ramps down volume on the record data, powers down the analog and digital blocks, and puts the device into hardware shutdown mode in 25 ms (typical).

    This implies that the device is placed in Hardware Shutdown only after the Volume is Ramped to zero. This means complete Shutdown using the SHDNZ pin shall take at least 25ms.

    ---------------------------------------------------

    Asserting The ShDZN pin is the equivalent of a Hardware Reset. This is because the Digital  Block is shut down on asserting. On Bringing into life the initial Boot sequence happens.

    ----------------------------------------------- 

    You should asset SHTZN When you like to go into a very low power mode where the device consumes less then 0.1ua of current.

    --------------------------------------------------

    Normally these chips are very stable if you sequence the power during on and off as specified .

    In addition the only change while working is the removal and connection of the Timing Data on the Fly.On removal of the timing the ADC Channels powers off. On connection of the timing the chip autodetects the timings. Normally this should happen without problem. But its always good to check this on a system level .