This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TLV320AIC3262: Configuration of TLV320AIC3262 as Master mode

Part Number: TLV320AIC3262

Hi, 

We are using tlv320aic3262 codec for our platform. We wanted to ser TLV codec as a master and I2S as slave,

We didrequired devce tree on linux kernel changes as mentioned below

 sound0: sound0 {
                compatible = "simple-audio-card";
                simple-audio-card,name = "tlv320aic3262-hifi";
                simple-audio-card,format = "i2s";
                simple-audio-card,bitclock-master = <&sound_master>;
                simple-audio-card,frame-master = <&sound_master>;
                simple-audio-card,cpu {
                        sound-dai = <&i2s0>;
                        //dai-tdm-slot-num = <2>;
                };
                sound_master: simple-audio-card,codec {
                        sound-dai = <&tlv320aic3262>;
                        system-clock-frequency = <12288000>;
                };
        };
&i2c1 {
        status = "okay";
        tlv320aic3262: codec@18 {
                compatible = "ti,aic3262";
                reg = <0x18>;
                #sound-dai-cells= <0>;
                status = "okay";
        };
};
 
OUTPUTS:
[    6.188897] *********** TLV Codec Master  mode****************
[    6.188900] *********** TLV Codec Right J****************
[    6.198037] ******I2S-C Slave***** cdns_i2s_set_fmt 409 sound/soc/cadence/cadence-i2s.c
[    6.211552] ******I2S-C I2S Normal***** cdns_i2s_set_fmt 458 sound/soc/cadence/cadence-i2s.c
After doing this we are not able capture or playback any wav file, we are suspecting that master not able to generate the clock.
I have attached the shell script for all the codec register setting.
#########################################
#codec-18.sh 
#########################################
#Software reset
i2cset -f -y 2 0x19 0x0 0x0
i2cset -f -y 2 0x19 0x7f 0x0
i2cset -f -y 2 0x19 0x1 0x1

#clock configuration(same for asi1 & as2)
i2cset -f -y 2 0x19 0x0 0x0
i2cset -f -y 2 0x19 0x4 0x0
i2cset -f -y 2 0x19 0xb 0x81
i2cset -f -y 2 0x19 0xc 0x82
i2cset -f -y 2 0x19 0xd 0x00
i2cset -f -y 2 0x19 0xe 0x80

i2cset -f -y 2 0x19 0x12 0x81
i2cset -f -y 2 0x19 0x13 0x82
i2cset -f -y 2 0x19 0x14 0x80

#power & analog configuration
i2cset -f -y 2 0x19 0x0 0x1
i2cset -f -y 2 0x19 0x1 0x0
i2cset -f -y 2 0x19 0x7a 0x1
i2cset -f -y 2 0x19 0x79 0x33 # ref charging time 

#audio serial interface routing configuration for ASI1
i2cset -f -y 2 0x19 0x0 0x4
i2cset -f -y 2 0x19 0x1 0x00
i2cset -f -y 2 0x19 0x8 0xf0
i2cset -f -y 2 0x19 0xa 0x24 # Master mode set for B0_P4_R10

#signal processing setting
i2cset -f -y 2 0x19 0x0 0x0
i2cset -f -y 2 0x19 0x3c 0x1
i2cset -f -y 2 0x19 0x3d 0x1 


#output channel configuration
i2cset -f -y 2 0x19 0x0 0x1
i2cset -f -y 2 0x19 0x3 0x0
i2cset -f -y 2 0x19 0x4 0x0
i2cset -f -y 2 0x19 0x1b 0x30 

i2cset -f -y 2 0x19 0x0 0x0
i2cset -f -y 2 0x19 0x3f 0xc0

i2cset -f -y 2 0x19 0x0 0x1
i2cset -f -y 2 0x19 0x1f 0xb9
i2cset -f -y 2 0x19 0x20 0xb9

i2cset -f -y 2 0x19 0x21 0x28 
i2cset -f -y 2 0x19 0x22 0x3e
i2cset -f -y 2 0x19 0x23 0x30
i2cset -f -y 2 0x19 0x1f 0x80 # 
i2cset -f -y 2 0x19 0x20 0x80

i2cset -f -y 2 0x19 0x0 0x0
i2cset -f -y 2 0x19 0x40 0x40

i2cset -f -y 2 0x19 0x0 0x1
i2cset -f -y 2 0x19 0x09 0x70
i2cset -f -y 2 0x19 0x1b 0x33

i2cset -f -y 2 0x19 0x0 0x1
i2cset -f -y 2 0x19 0x09 0x10

#adc config
i2cset -f -y 2 0x19 0x0 0x1
i2cset -f -y 2 0x19 0x8 0x0
i2cset -f -y 2 0x19 0x34 0x20 #diff
i2cset -f -y 2 0x19 0x36 0x80
i2cset -f -y 2 0x19 0x37 0x20 #diff
i2cset -f -y 2 0x19 0x39 0x80
i2cset -f -y 2 0x19 0x3b 0x0c #diff
i2cset -f -y 2 0x19 0x3c 0x0c #diff
i2cset -f -y 2 0x19 0x3d 0x0

i2cset -f -y 2 0x19 0x0 0x0
i2cset -f -y 2 0x19 0x51 0xc0
i2cset -f -y 2 0x19 0x52 0x0
Thanks & BR
Rizwan Chikodi
  • Hi,

    From your register settings with MCLK1=12.288MHz you should see WCLK1 of 48KHz and BCLK1 of 3.072MHz, did you see that on the scope?

    Your settings are similar to the example in section 4.1.1 of this reference guide except it's slave mode so it should work.

    https://www.ti.com/lit/ug/slau309/slau309.pdf?ts=1676585354030&ref_url=https%253A%252F%252Fwww.ti.com%252Fproduct%252FTLV320AIC3262

    #########################################
    #codec-18.sh 
    #########################################
    #Software reset
    i2cset -f -y 2 0x19 0x0 0x0
    i2cset -f -y 2 0x19 0x7f 0x0
    i2cset -f -y 2 0x19 0x1 0x1
    
    #clock configuration(same for asi1 & as2)
    i2cset -f -y 2 0x19 0x0 0x0
    i2cset -f -y 2 0x19 0x4 0x0 # DAC_CLKIN=ADC_CLKIN=MCLK1
    i2cset -f -y 2 0x19 0xb 0x81 # NDAC powered and NDAC=1
    i2cset -f -y 2 0x19 0xc 0x82 # MDAC powered and MDAC=2
    i2cset -f -y 2 0x19 0xd 0x00 # 
    i2cset -f -y 2 0x19 0xe 0x80 # DOSR=128
    
    i2cset -f -y 2 0x19 0x12 0x81 # NADC powered and NADC=1
    i2cset -f -y 2 0x19 0x13 0x82 # MADC powered and MADC=2
    i2cset -f -y 2 0x19 0x14 0x80 # AOSR=128
    
    #power & analog configuration
    i2cset -f -y 2 0x19 0x0 0x1
    i2cset -f -y 2 0x19 0x1 0x0
    i2cset -f -y 2 0x19 0x7a 0x1 # Ref power up delay
    i2cset -f -y 2 0x19 0x79 0x33 # ref charging time 1.1ms
    
    #audio serial interface routing configuration for ASI1
    i2cset -f -y 2 0x19 0x0 0x4 
    i2cset -f -y 2 0x19 0x1 0x00 # ASI1=I2S, 16 bits
    i2cset -f -y 2 0x19 0x8 0xf0 # ASI1 Left and Right DAC mixed of Left and Right data
    i2cset -f -y 2 0x19 0xa 0x24 # Master mode 
    
    #signal processing setting
    i2cset -f -y 2 0x19 0x0 0x0
    i2cset -f -y 2 0x19 0x3c 0x1 # PRB_P1
    i2cset -f -y 2 0x19 0x3d 0x1 # PRB_R1
    
    
    #output channel configuration
    i2cset -f -y 2 0x19 0x0 0x1
    i2cset -f -y 2 0x19 0x3 0x0 # Left DAC in PTM_P3_P4
    i2cset -f -y 2 0x19 0x4 0x0 # Right DAC in PTM_P3_P4
    i2cset -f -y 2 0x19 0x1b 0x30 # Left DAC to HPL and Right DAC to HPR and powered down
    
    i2cset -f -y 2 0x19 0x0 0x0
    i2cset -f -y 2 0x19 0x3f 0xc0 # Left and Right DAC powered up
    
    i2cset -f -y 2 0x19 0x0 0x1
    i2cset -f -y 2 0x19 0x1f 0xb9 # HP Ground_Centered and HPL volume is muted
    i2cset -f -y 2 0x19 0x20 0xb9 # HPR=HPL and HPR volume is muted
    
    i2cset -f -y 2 0x19 0x21 0x28 # CP clock divide=4 default
    i2cset -f -y 2 0x19 0x22 0x3e # CP default
    i2cset -f -y 2 0x19 0x23 0x30 # CP auto power up
    i2cset -f -y 2 0x19 0x1f 0x80 # HP Ground_Centered and volume is 0dB
    i2cset -f -y 2 0x19 0x20 0x80 # HPR=HPL and HPR volume is 0dB
    
    i2cset -f -y 2 0x19 0x0 0x0
    i2cset -f -y 2 0x19 0x40 0x40 # Left and Right DAC not muted
    
    i2cset -f -y 2 0x19 0x0 0x1
    i2cset -f -y 2 0x19 0x09 0x70 # HP 25%
    i2cset -f -y 2 0x19 0x1b 0x33 # Left DAC to HPL and Right DAC to HPR and powered up
    
    i2cset -f -y 2 0x19 0x0 0x1
    i2cset -f -y 2 0x19 0x09 0x10 # HP 100%
    
    #adc config
    i2cset -f -y 2 0x19 0x0 0x1
    i2cset -f -y 2 0x19 0x8 0x0 # VOCM= Input CM
    i2cset -f -y 2 0x19 0x34 0x20 # IN2L P-Term 20K on Left_ADC
    i2cset -f -y 2 0x19 0x36 0x80 # CM 20K on M-Term on Left_ADC
    i2cset -f -y 2 0x19 0x37 0x20 # IN2R P-Term 20K on Right_ADC
    i2cset -f -y 2 0x19 0x39 0x80 # CM 20K on M-Term on Right_ADC
    i2cset -f -y 2 0x19 0x3b 0x0c # Left_ADC enabled with 6dB
    i2cset -f -y 2 0x19 0x3c 0x0c # Right_ADC enabled with 6dB
    i2cset -f -y 2 0x19 0x3d 0x0 # Default ADC PowerTune
    
    i2cset -f -y 2 0x19 0x0 0x0
    i2cset -f -y 2 0x19 0x51 0xc0 # Left and Right ADC powered up
    i2cset -f -y 2 0x19 0x52 0x0 # Left and Right ADC not muted

    So check the clocks on your setup to start with.

    Regards.

  • Hi,

    I tried probing the WCLK and BCLK but I'm not able see any clocks generation on oscilloscope.

    I have attached the snap shot of waveform

      

    Thanks & BR

  • Hi, 

    Have you checked MCLK is present in the scope and codec is found as the soundcard?

    Shenghao,

    Can you help with the Linux side? The configuration is correct but there's no clock coming up from the codec. 

    Regards.

  • Hi pdjuandi 

    We have verified earlier I2S controller as Master and TLV320 as slave, Its workingfine. It means codec is getting MCLK.

    But when configuring TLV320 codec is found as a master and I2S controller as slave we found the soundcard card register successfully but not able see the BCLK and WCLK clock.

    Also We are getting input/output error while arecord and aplay as mentioned below

    arecord -Dhw:0,0 -f S16_LE -r 44100 -c 2 Codec-master.wav

    aplay -Dhw:0,0 -f S16_LE -r 44100 -c 2 Codec-master.wav

    Sound card detection:

    [ 6.760529] ALSA device list:
    [ 6.763527] #0: tlv320aic3262-hifi
    [ 6.767123] #1: nb2,pdm-mic1
    [ 6.770184] #2: nb2,sdac-playback

    Thanks and BR

  • Hi,

    For master mode, we need to make sure MCLK is correct. Can you capture MCLK with scope?

    Please provide the Linux error so our FW team can help analyze it.

    Regards.

  • Sure Will provide more information on this.

  • Hi...

    I have mentioned the input output error below

    root@:~# aplay -Dhw:0,0 /usr/share/sounds/alsa/*
    Playing WAVE '/usr/share/sounds/alsa/Front_Center.wav' : Signed 16 bit Little Endian, Rate 48000 Hz, Mono
    aplay: pcm_write:2059: write error: Input/output error
    root@:~#

    For Measuring Audio MCLK clock, we need to do some hardware modification once we done will capture waveform and send you asap.

    Thanks very much

  • OK, I have requested our Linux expert to comment on the error.

  • Hi, Rizwan

    Peter has offer the i2C script to config master mode for the code, can you offer MCLK, WS clk and bit clk in the same plot with the scope.

    In my view, if mlck is on with the i2c script, the codec should be work well. If this work well, we can check the code.

    BR

    Shenghao Ding

  • Hi Shenghao

    I have checked with AUDIO MCLK, BCLK and WCLK.

    I'm able see the AUDIO MCLK clock waveform on scope as mentioned below

    And not able to see the BCLK and WCLK clock on scope

    Thanks very much

    Rizwan Chikodi

  • Just confirm from you whether all the plots are captured after running the i2c script instead of the code, right? 

  • Kindly dump the register during running that i2c script.

    One more thing, there are three MCLK pins, they are mclk1/mclk2/mclk3, which one did you measure?

    As to bck and wsclk pin, there're still three groups. which group do you measure?

  • I2C dump register details:

    After running the i2c script

    root@codec18-configs# i2cdump -f -y 2 0x18
    No size specified (using byte-data access)
    0 1 2 3 4 5 6 7 8 9 a b c d e f 0123456789abcdef
    00: 00 00 b0 00 00 00 11 04 00 00 01 81 82 00 80 00 ..?...??..???.?.
    10: 00 00 81 82 80 00 01 01 0f 80 00 18 6a 20 00 06 ..???.????.?j .?
    20: 1a 00 00 00 cc 88 ee 00 00 00 00 00 00 00 00 00 ?...???.........
    30: 00 00 00 00 00 00 00 00 00 00 00 00 01 01 00 c0 ............??.?
    40: 40 00 00 00 6f 00 00 00 00 00 00 ee 10 d8 7e e3 @...o......???~?
    50: 00 c0 00 00 00 00 00 00 7f 00 00 00 00 00 00 00 .?......?.......
    60: 7f 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ?...............
    70: 00 00 00 00 00 00 00 00 00 00 00 00 00 03 01 00 .............??.
    80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
    90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
    a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
    b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
    c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
    d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
    e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
    f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
    (failed reverse-i-search)`aplay': cd ^Cdio/
    root@codec18-configs# aplay -Dhw:0,0 /usr/share/sounds/alsa/* &
    [1] 552
    Playing WAVE '/usr/share/sounds/alsa/Front_Center.wav' : Signed 16 bit Little Endian, Rate 48000 Hz, Mono
    root@codec18-configs#
    root@codec18-configs# i2cdump -f -y 2 0x18
    No size specified (using byte-data access)
    0 1 2 3 4 5 6 7 8 9 a b c d e f 0123456789abcdef
    00: 00 00 b0 00 00 00 11 04 00 00 01 81 82 00 80 00 ..?...??..???.?.
    10: 00 00 81 82 80 00 01 01 0f 80 00 18 6a 20 00 06 ..???.????.?j .?
    20: 1a 00 00 00 cc 88 ee 00 00 00 00 00 00 00 00 00 ?...???.........
    30: 00 00 00 00 00 00 00 00 00 00 00 00 01 01 00 c0 ............??.?
    40: 40 00 00 00 6f 00 00 00 00 00 00 ee 10 d8 7e e3 @...o......???~?
    50: 00 c0 00 00 00 00 00 00 7f 00 00 00 00 00 00 00 .?......?.......
    60: 7f 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ?...............
    70: 00 00 00 00 00 00 00 00 00 00 00 00 00 03 01 00 .............??.
    80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
    90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
    a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
    b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
    c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
    d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
    e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
    f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
    root@codec18-configs# aplay: pcm_write:2059: write error: Input/output error

    [1]+ Done(1) aplay -Dhw:0,0 /usr/share/sounds/alsa/*

    We have measured MCLK1 BCLK1 and WCLK1.

    For MCLK1 we are able see the clock on scope. But for BCLK1 and WCLK1 there is no clock signals.

    Thanks & Regards

    Rizwan Chikodi

  • Kindly offer book0 page4 register dump

  • Hi Shenghao,

    For Book0 and Page 4 we are setting only below register's

    i2cset -f -y 2 0x18 0x0 0x4
    i2cset -f -y 2 0x18 0x1 0x00
    i2cset -f -y 2 0x18 0x8 0xf0
    i2cset -f -y 2 0x18 0xa 0x24

    You mean we need to set B0_P4_R86_D[6:2] register also ?

    Thanks very much

  • according to the datasheet, it will do.

  • we need set only this B0_P4_R86_D[6:2] register through i2cset ?

    if yes, the value 0x86 is ?

  • Let me check internally.

  • Hello Rizwan, 

    It seems that we cannot find an issue on the software/firmware side at this moment. I would like to check if we can find an issue with the hardware. What pins are you measuring for each clock? Would it be possible to share a schematic, application diagram and/or test set-up? 

    If possible, a good next step would be using a logic analyzer to see what data is showing up when measured directly at each pin when writing an I2C command. Let me know if this is a possibility.

    Best,
    Andrew

  • Hi Andrew Jackiw

    I will discuss with our internal team get back to you as soon as possible.

    Thanks very much

    Rizwan

  • Rizwan,

    Thank you for your patience in solving this issue. I look forward to your response.

    -Andrew

  • Hi Andrew Jackiw

    I was busy with Headphone mic support ticket.

    I have started working on this ticket now, I will share you schematic asap

    Thanks and BR

    Rizwan Chikodi

  • Hi Andrew Jackiw

    I have attached the audio daughter card schematic pdf. please check and let me know anything more needed.

    Thanks

    Rizwan

  • Not able to attach the schematic pdf here.

  • Hi Rizwan,

    Are the I2C pins connected to pull up resistors? Can you follow Andrew's suggestion and measure an I2C transaction? Specifically that a write and read is valid?

    Thank you,

    Jeff McPherson

  • Hi Jeff McPherson,

    The I2C pull-up resistors are DNP (Not populated).

    Still i need to check i2c transaction for read and write without i2c pull up resistors ?

    Thanks & BR

    Rizwan

  • Hi Rizwan,

    Without pull-up resistors, the I2C bus will not function. They need to be populated.

    Best regards,

    Jeff McPherson

  • Hi Jeff

    I have populated i2c connections, still not able capture or playback the audio.

    Observations:

    -----------------------------------------------------------------------------------------------------------
    [ 6.623768] *********** TLV Codec Master mode****************
    [ 6.623772] *********** TLV Codec Right J****************
    [ 6.633084] ******I2S-C Slave***** cdns_i2s_set_fmt 409 sound/soc/cadence/cadence-i2s.c
    [ 6.646612] ******I2S-C I2S Normal***** cdns_i2s_set_fmt 458 sound/soc/cadence/cadence-i2s.c
    [ 6.738817] cfg80211: Loading compiled-in X.509 certificates for regulatory database
    [ 6.760459] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
    [ 6.767259] ALSA device list:
    [ 6.770240] #0: tlv320aic3262-hifi
    [ 6.776919] #2: sdac-playback

    -----------------------------------------------------------------------------------------------------------
    I2C read/write operation
    -----------------------------------------------------------------------------------------------------------
    root@:~# i2cset -f -y 2 0x18 0xa 0x24
    root@:~# i2cget -f -y 2 0x18 0xa
    0x24
    root@:~#
    -----------------------------------------------------------------------------------------------------------

    root@:~# arecord -l
    **** List of CAPTURE Hardware Devices ****
    card 0: tlv320aic3262hi [tlv320aic3262-hifi], device 0: 300080000.i2s0-aic326x-asi1 aic326x-asi1-0 [300080000.i2s0-aic326x-asi1 aic326x-asi1-0]
    Subdevices: 1/1
    Subdevice #0: subdevice #0
    -----------------------------------------------------------------------------------------------------------
    root@:~# aplay -Dhw:0,0 /usr/share/sounds/alsa/*
    Playing WAVE '/usr/share/sounds/alsa/Front_Center.wav' : Signed 16 bit Little Endian, Rate 48000 Hz, Mono
    aplay: pcm_write:2059: write error: Input/output error
    -----------------------------------------------------------------------------------------------------------

    After running the shell script dump register details are mentioned below
    -----------------------------------------------------------------------------------------------------------
    root@:~# i2cdump -f -y 2 0x18
    No size specified (using byte-data access)
    0 1 2 3 4 5 6 7 8 9 a b c d e f 0123456789abcdef
    00: 00 00 b0 00 00 00 11 04 00 00 01 81 82 00 80 00 ..?...??..???.?.
    10: 00 00 81 82 80 00 01 01 0f 80 00 18 6a 20 00 06 ..???.????.?j .?
    20: 1a 00 00 00 cc 88 ff 00 00 00 00 00 00 00 00 00 ?...??..........
    30: 00 00 00 00 00 00 00 00 00 00 00 00 01 01 00 c0 ............??.?
    40: 4c 00 00 00 6f 00 00 00 00 00 00 ee 10 d8 7e e3 L...o......???~?
    50: 00 c0 00 00 00 00 00 00 7f 00 00 00 00 00 00 00 .?......?.......
    60: 7f 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ?...............
    70: 00 00 00 00 00 00 00 00 00 00 00 00 00 03 01 00 .............??.
    80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
    90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
    a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
    b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
    c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
    d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
    e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
    f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................

    -----------------------------------------------------------------------------------------------------------

    I'm suspecting that the issue could be in register setting, Please Let me know your thoughts.

    I have attached the shell script.

    #########################################
    #codec-18.sh 
    #########################################
    #Software reset
    i2cset -f -y 2 0x18 0x0 0x0
    i2cset -f -y 2 0x18 0x7f 0x0
    i2cset -f -y 2 0x18 0x1 0x1
    
    #clock configuration(same for asi1 & as2)
    i2cset -f -y 2 0x18 0x0 0x0
    i2cset -f -y 2 0x18 0x4 0x0 # DAC_CLKIN=ADC_CLKIN=MCLK1
    i2cset -f -y 2 0x18 0xb 0x81 # NDAC powered and NDAC=1
    i2cset -f -y 2 0x18 0xc 0x82 # MDAC powered and MDAC=2
    i2cset -f -y 2 0x18 0xd 0x00 # 
    i2cset -f -y 2 0x18 0xe 0x80 # DOSR=128
    
    i2cset -f -y 2 0x18 0x12 0x81 # NADC powered and NADC=1
    i2cset -f -y 2 0x18 0x13 0x82 # MADC powered and MADC=2
    i2cset -f -y 2 0x18 0x14 0x80 # AOSR=128
    
    #power & analog configuration
    i2cset -f -y 2 0x18 0x0 0x1
    i2cset -f -y 2 0x18 0x1 0x0
    i2cset -f -y 2 0x18 0x7a 0x1 # Ref power up delay
    i2cset -f -y 2 0x18 0x79 0x33 # ref charging time 1.1ms
    
    #audio serial interface routing configuration for ASI1
    i2cset -f -y 2 0x18 0x0 0x4 
    i2cset -f -y 2 0x18 0x1 0x00 # ASI1=I2S, 16 bits
    i2cset -f -y 2 0x18 0x8 0xf0 # ASI1 Left and Right DAC mixed of Left and Right data
    i2cset -f -y 2 0x18 0xa 0x24 # Master mode 
    
    #signal processing setting
    i2cset -f -y 2 0x18 0x0 0x0
    i2cset -f -y 2 0x18 0x3c 0x1 # PRB_P1
    i2cset -f -y 2 0x18 0x3d 0x1 # PRB_R1
    
    
    #output channel configuration
    i2cset -f -y 2 0x18 0x0 0x1
    i2cset -f -y 2 0x18 0x3 0x0 # Left DAC in PTM_P3_P4
    i2cset -f -y 2 0x18 0x4 0x0 # Right DAC in PTM_P3_P4
    i2cset -f -y 2 0x18 0x1b 0x30 # Left DAC to HPL and Right DAC to HPR and powered down
    
    i2cset -f -y 2 0x18 0x0 0x0
    i2cset -f -y 2 0x18 0x3f 0xc0 # Left and Right DAC powered up
    
    i2cset -f -y 2 0x18 0x0 0x1
    i2cset -f -y 2 0x18 0x1f 0xb9 # HP Ground_Centered and HPL volume is muted
    i2cset -f -y 2 0x18 0x20 0xb9 # HPR=HPL and HPR volume is muted
    
    i2cset -f -y 2 0x18 0x21 0x28 # CP clock divide=4 default
    i2cset -f -y 2 0x18 0x22 0x3e # CP default
    i2cset -f -y 2 0x18 0x23 0x30 # CP auto power up
    i2cset -f -y 2 0x18 0x1f 0x80 # HP Ground_Centered and volume is 0dB
    i2cset -f -y 2 0x18 0x20 0x80 # HPR=HPL and HPR volume is 0dB
    
    i2cset -f -y 2 0x18 0x0 0x0
    i2cset -f -y 2 0x18 0x40 0x40 # Left and Right DAC not muted
    
    i2cset -f -y 2 0x18 0x0 0x1
    i2cset -f -y 2 0x18 0x09 0x70 # HP 25%
    i2cset -f -y 2 0x18 0x1b 0x33 # Left DAC to HPL and Right DAC to HPR and powered up
    
    i2cset -f -y 2 0x18 0x0 0x1
    i2cset -f -y 2 0x18 0x09 0x10 # HP 100%
    
    #adc config
    i2cset -f -y 2 0x18 0x0 0x1
    i2cset -f -y 2 0x18 0x8 0x0 # VOCM= Input CM
    i2cset -f -y 2 0x18 0x34 0x20 # IN2L P-Term 20K on Left_ADC
    i2cset -f -y 2 0x18 0x36 0x80 # CM 20K on M-Term on Left_ADC
    i2cset -f -y 2 0x18 0x37 0x20 # IN2R P-Term 20K on Right_ADC
    i2cset -f -y 2 0x18 0x39 0x80 # CM 20K on M-Term on Right_ADC
    i2cset -f -y 2 0x18 0x3b 0x0c # Left_ADC enabled with 6dB
    i2cset -f -y 2 0x18 0x3c 0x0c # Right_ADC enabled with 6dB
    i2cset -f -y 2 0x18 0x3d 0x0 # Default ADC PowerTune
    
    i2cset -f -y 2 0x18 0x0 0x0
    i2cset -f -y 2 0x18 0x51 0xc0 # Left and Right ADC powered up
    i2cset -f -y 2 0x18 0x52 0x0 # Left and Right ADC not muted

    Thanks and Regards

    Rizwan Chikodi

  • Hello Rizwan,

    Sorry for the delay. While I review the register settings. Please see the below recommendations / questions.

    • Please check the connections in the schematic. Depending on the software used these would be considered not connected. Although unlikely, please confirm that each color connection is connected in the layout/PCB.

    • Please perform a single I2C write and then read the register to confirm the I2C bus is working. The terminal shows a line that says "write error
      root@:~# aplay -Dhw:0,0 /usr/share/sounds/alsa/*
      Playing WAVE '/usr/share/sounds/alsa/Front_Center.wav' : Signed 16 bit Little Endian, Rate 48000 Hz, Mono
      aplay: pcm_write:2059: write error: Input/output error
    • Please provide a scope capture of MCLK as requested previously.
    • Please move the "#adc config" block of the script before the "#output channel configuration"
    • These test scripts have the correct power sequencing for the clock dividers.
      • Dividers should be powered up as follows: 'PLL' > 'NDAC / NADC' > 'MDAC / MADC'. 
      • Your script currently does not follow this sequence.

    Best,
    Andrew

  • Hi Andrew Jackiw

    • In PCB all mentioned connection are connected and verified connectivity.
    • I2C read/ write operation is working as i mentioned earlier.
      • root@:~# i2cset -f -y 2 0x18 0xa 0x24
        root@:~# i2cget -f -y 2 0x18 0xa
        0x24
    • We are able see the MCLK1 clock as mentioned above
      •   
      • But not able see the clock signal for BCLK and WCLK lines.
    • I have checked as per your suggestion by adding adc config block before output channel configurations
      • #########################################
        #codec-18.sh 
        #########################################
        #Software reset
        i2cset -f -y 2 0x18 0x0 0x0
        i2cset -f -y 2 0x18 0x7f 0x0
        i2cset -f -y 2 0x18 0x1 0x1
        
        #clock configuration(same for asi1 & as2)
        i2cset -f -y 2 0x18 0x0 0x0
        i2cset -f -y 2 0x18 0x4 0x0 # DAC_CLKIN=ADC_CLKIN=MCLK1
        i2cset -f -y 2 0x18 0xb 0x81 # NDAC powered and NDAC=1
        i2cset -f -y 2 0x18 0xc 0x82 # MDAC powered and MDAC=2
        i2cset -f -y 2 0x18 0xd 0x00 # 
        i2cset -f -y 2 0x18 0xe 0x80 # DOSR=128
        
        i2cset -f -y 2 0x18 0x12 0x81 # NADC powered and NADC=1
        i2cset -f -y 2 0x18 0x13 0x82 # MADC powered and MADC=2
        i2cset -f -y 2 0x18 0x14 0x80 # AOSR=128
        
        #power & analog configuration
        i2cset -f -y 2 0x18 0x0 0x1
        i2cset -f -y 2 0x18 0x1 0x0
        i2cset -f -y 2 0x18 0x7a 0x1 # Ref power up delay
        i2cset -f -y 2 0x18 0x79 0x33 # ref charging time 1.1ms
        
        #audio serial interface routing configuration for ASI1
        i2cset -f -y 2 0x18 0x0 0x4 
        i2cset -f -y 2 0x18 0x1 0x00 # ASI1=I2S, 16 bits
        i2cset -f -y 2 0x18 0x8 0xf0 # ASI1 Left and Right DAC mixed of Left and Right data
        i2cset -f -y 2 0x18 0xa 0x24 # Master mode 
        
        #signal processing setting
        i2cset -f -y 2 0x18 0x0 0x0
        i2cset -f -y 2 0x18 0x3c 0x1 # PRB_P1
        i2cset -f -y 2 0x18 0x3d 0x1 # PRB_R1
        
        #adc config
        i2cset -f -y 2 0x18 0x0 0x1
        i2cset -f -y 2 0x18 0x8 0x0 # VOCM= Input CM
        i2cset -f -y 2 0x18 0x34 0x20 # IN2L P-Term 20K on Left_ADC
        i2cset -f -y 2 0x18 0x36 0x80 # CM 20K on M-Term on Left_ADC
        i2cset -f -y 2 0x18 0x37 0x20 # IN2R P-Term 20K on Right_ADC
        i2cset -f -y 2 0x18 0x39 0x80 # CM 20K on M-Term on Right_ADC
        i2cset -f -y 2 0x18 0x3b 0x0c # Left_ADC enabled with 6dB
        i2cset -f -y 2 0x18 0x3c 0x0c # Right_ADC enabled with 6dB
        i2cset -f -y 2 0x18 0x3d 0x0 # Default ADC PowerTune
        
        i2cset -f -y 2 0x18 0x0 0x0
        i2cset -f -y 2 0x18 0x51 0xc0 # Left and Right ADC powered up
        i2cset -f -y 2 0x18 0x52 0x0 # Left and Right ADC not muted
        
        #output channel configuration
        i2cset -f -y 2 0x18 0x0 0x1
        i2cset -f -y 2 0x18 0x3 0x0 # Left DAC in PTM_P3_P4
        i2cset -f -y 2 0x18 0x4 0x0 # Right DAC in PTM_P3_P4
        i2cset -f -y 2 0x18 0x1b 0x30 # Left DAC to HPL and Right DAC to HPR and powered down
        
        i2cset -f -y 2 0x18 0x0 0x0
        i2cset -f -y 2 0x18 0x3f 0xc0 # Left and Right DAC powered up
        
        i2cset -f -y 2 0x18 0x0 0x1
        i2cset -f -y 2 0x18 0x1f 0xb9 # HP Ground_Centered and HPL volume is muted
        i2cset -f -y 2 0x18 0x20 0xb9 # HPR=HPL and HPR volume is muted
        
        i2cset -f -y 2 0x18 0x21 0x28 # CP clock divide=4 default
        i2cset -f -y 2 0x18 0x22 0x3e # CP default
        i2cset -f -y 2 0x18 0x23 0x30 # CP auto power up
        i2cset -f -y 2 0x18 0x1f 0x80 # HP Ground_Centered and volume is 0dB
        i2cset -f -y 2 0x18 0x20 0x80 # HPR=HPL and HPR volume is 0dB
        
        i2cset -f -y 2 0x18 0x0 0x0
        i2cset -f -y 2 0x18 0x40 0x40 # Left and Right DAC not muted
        
        i2cset -f -y 2 0x18 0x0 0x1
        i2cset -f -y 2 0x18 0x09 0x70 # HP 25%
        i2cset -f -y 2 0x18 0x1b 0x33 # Left DAC to HPL and Right DAC to HPR and powered up
        
        i2cset -f -y 2 0x18 0x0 0x1
        i2cset -f -y 2 0x18 0x09 0x10 # HP 100%
        
    • Please let us know if we missed any information need to be passed.
    • Still we are getting input output error running aplay command.

    Thanks and BR

    Rizwan Chikodi

  • Rizwan,

    Your configuration looks correct for I2S as master with a Fs = 48kHz Fs. Can you confirm the MCLK frequency and shape? The MCLK looks like a triangle waveform, it is generally reccomended that MCLK has a Duty Cycle of ~50%. Is this caused by scope BW? Can you make sure it's 50% DC 12.2876MHz square wave?

    Also please check the supplies. Are all supplies like DVDD, IOVDD up and stable?

    Please also read back registers B0_P4_R65 and B0_P4_R10?

    Best,
    Andrew

  • Hi Andrew

    • Im not sure how check square wave form for MCLK1 clock 

               We are using dwinstek oscilloscope.

    • I have measured DVDD and IOVDD supply its 1.8volt.

    ---------- B0_P4_R65 -----------------
    root@:~# i2cset -f -y 2 0x18 0x0 0x4
    root@:~# i2cget -f -y 2 0x18 0x41
    0x04
    root@:~#

    -----------B0_P4_R10------------------
    root@:~# i2cset -f -y 2 0x18 0x0 0x4
    root@:~# i2cget -f -y 2 0x18 0x0A
    0x24
    root@:~#

    Thanks very much

    Rizwan Chikodi

  • Hello Rizwan,

    Thank you for your inputs this far. From your register configurations we expect to see WCLK and BCLK as outputs from the device. Judging from your scope's settings and capabilities, the waveform is represented correctly as a triangle-shaped wave form. At this time, we have two suggestions/recommendations.

    1. MCLK may need to be disabled while I2C writes are configuring the device. Please enable MCLK after the device is fully configured and probe WCLK and BCLK again.
    2. MCLK is not valid, and a more square-shaped wave form is needed for the device to operate correctly. Please provide a MCLK that is a 50% duty cycle square wave to the device. 

    Try implementing item #1 alone first and then #1 and #2 together. This will help isolate if the MCLK is the issue. 

    Best,
    Andrew