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TLV320DAC3100: How to configure for use without MCLK and output to speaker?

Jochem van Kranenburg
Prodigy 100 points
Part Number: TLV320DAC3100


Hi there,

We've selected the TLV320DAC3100 as possible succesor of one of our previously selected I2S amplifiers as its features are so extensive. A little background information; we're using an nRF52840 as I2S master which can only provide a BCLK, WCLK and DIN signal. This is configured through the Zephyr driver listed here. I don't need help with how to use the API, as that's out of your scope, but I would like help with configuring the chip for use in the following scenario.

  1. I would like to play a 32kHz, mono, 16-bit audio source without using the MCLK. How would I need to configure the PLL_CLK, CODEC_CLK, MDAC, NDAC, OSR and MOD_CLK? I've thrown a little to many hours to it and can't help but feel frustrated that I haven't figured this out.
  2. I also couldn't figure out how to route the audio to both, the headphones and speaker. Does that need to go through the mixing amplifier?

I've only managed to get distorted audio (with question 1 as result) through only the headphones and not the speakers (with question 2 as result).

Any help is greatly appreciated.

Kind regards,

Jochem

  • 0
    TI__Guru** 110125 points

    Hi Jochem,

    Based on your description I assume the following, can you confirm it's correct?:

    • WCLK = 32kHz
    • BCLK = 32k * 16-bit * 2-channels = 1.024MHz

    Even though you mentioned mono, since this is I2S data I would still expect 2 channels being sent over the audio serial interface, then you would only use left-channel data as input to the DAC.
    If the above is correct, you may be able to use the following clock settings:

    • PLL_P = 1
    • PLL_R = 2
    • PLL_J = 40
    • PLL_D = 0
    • NDAC = 4
    • MDAC = 5
    • DOSR = 128
    • Make sure register 0x04 = 0x07 to select BCLK as input to PLL, and PLL output as input to CODEC_CLKIN
    • Please note that if you halt the clocks at any point after clock initialization, you may have to re-initialize as the device may detect the missing clocks as an error.

    Regarding DAC signal routing, you should do the following:

    • Page 1 Register 0x23 = 0x40 so that DAC_L is routed to the left-channel mixer amplifier.
    • Page 1 Registers 0x24, 0x25 and 0x26 = 0x80 so that MSB is enabled to route the analog PGA to each of the output drivers. Note that Right DAC channel feeds Right-HP only, while Left DAC channel feeds both Left-HP and Class-D drivers.

    Hope this helps to keep your project moving, let us know if there are any further questions.

    Best regards,
    -Ivan Salazar
    Applications Engineer