PCM5142EVM-U: Registers configuration

Hi Danilo,

Can you elaborate on what your confusion is?

Thank you,

Jeff McPherson

Hi Arash,

Thank you for this explanation. Please see the follow up inquiry of our customer below.

Thanks for you answer but there is something i don't understand. I would like program a Fs = 48 [KHz] because at TP13 I have actually 44.1 [KHz] and I can't modify the parameter. Could you please give me the good registers ?

I'm a little lost because this frequency of 44.1 [KHz] comes from MCU, it means that MCU commands PCM5142 with this Fs and I don't want this one. I would like to work with 48 [KHz].

Regards,

Danilo

Hello Danilo,

If he is referring to the Test points on EVM, then he is measuring 44.1KHz  at TP13 which is SRC_LRCLK. Note   LRCLK that is coming out of TAS1020 (TP28)  needs to be checked as well . This LRCLK then goes to SRC4292 as  input and the  output is SRC_LRCLK which is TP13. So he needs to track back to see where the clk is changed. My guess is he is using a 22.5792MHz as MCLK instead of 24.576MHz and thus getting 44.1KHz.instead of 48KHz.

Note that EVM has a MCLK selector for SRC which selects b/w different MCLKs. Please check  the setting on that SW as well (Page 23 in User's guide).

Regards,

Arash

Hi Arash,

Our customer has a follow up inquiry below.

Thanks for your answer , I'll check and come back to you to say if it's good or not.

By the way if it's the solution for 48 [KHz] it's great but it's not possible to generate a sample rate like 96 or 192[KHz] ?

Regards,

Danilo

Hi Danilo, From what I see ,in the schematic, you can send your MCK of your choice using the same switches that I mentioned ( set the switch to HLL)

Regards

Arash

Hi Arash,

Please see the feedback of our customer below.

My last question is the next :

Like you know I'm programming the EvalBoard PCM5142EVM-U and for example I would like to get a sample rate of 192 [KHz]. I use your software CodecControl and there is the line who set the Fs (actually it is Fs = 96 [KHz]) because :

w E0 04 01 (this line is in the code called "PCM5101_USB_Playback") my screenshot"Register 04 Problem" show you the code.

And indeed the Fs is 96 [KHz] (because you divided by 256) . With this information I go check the datasheet of PCM5142 And I saw the this is not the good register like you can see (picture called : Register 04 problem 01). This register is about PLL so this is not the good register.

So with my intuition I changed w E0 04 01 for w E0 04 10 and indeed the sample rate changed to Fs = 192 [KHz].

I'm a little be lost because in the PCM5142's datasheet there is no relation with the register 04.
I see that the sofware I'm using is for PCM5101 (reference of his name "PCM5101_USB_Playback" ) but when I write in the register 04 it's still works on the PCM5142. Do you have the register map of PCM5101 ? Maybe it's useful.

Regards,

Danilo

Hello Danilo,

I do not see screenshots that he was referring to , but I think I can understand his issue without them.

He needs to go by the register map that is in PCM5142 datasheet , even though he might be using a different  GUI  from another device. 

Please note in Register 04, B1 is reserved  and he can not change it;  so when he changes the value of register 04 from 01 to 10  , he is only changing B0 from 1 to 0. Now lets look at B0 and what it does: 

 Bit0,  enables or disables the internal PLL. By  default PLL is enabled . Once  PLL is disabled, the master clock will be switched to the SCK.

Also please note that PCM5102 datasheet clearly specifies that  "SCK rates that are not common to standard audio clocks, between 1MHz and 50MHz, are only supported in software mode, available only in the PCM512x and PCM514x devices, by configuring various PLL and clock divider registers.

Regards,

Arash

Hi Arash,

I apologize that I forgot to attached the screenshots from the customer. Please see the screenshots below. There seems to be an error in the image you attached above. Can you please repost here? Thank you!

Regards,

Danilo

Hello Danilo,

The picture that didn't open correctly for you was in fact  table 58 that you  also have it above.  I think he is disabling the PLL by changing PLLE bit and thus master clk takes over. Once PLL is disabled , he can change master clk and see the effect. 

Regards,

Arash

Hi Arash,

Please see this update from our customer.

I load the code "PCM5101_USB Playback", I specify that I do not modify any line of the code.

If I read what is in register 04 I can see that the value read is:

As you can see, what is written and what is read are not the same thing.
And if I refer to the datasheet the bits are in these positions. 

This is not consistent. That's why I'm asking if there is not another document? Is the datasheet the right one?

Regards,

Danilo

Danilo,  Usually when a bit is reserved, it means you should not or could not write into it. You can READ it if you want but donot WRITE into it.

As I mentioned  before . we can   write in B0 (even B4 is read only but the device can write into it)  so  you can read it to see if PLL is locked or not- when applicable. 

So lets follow this procedure to find out what is going on with this register

start over and open up the GUI, READ register 04 . Note the values of  B0 and B4, then Change only B0 ( disable/enable PLL)  and then read it again to see if it is writing correctly.

So he should add the following 3 lines to the script:

r device_address  registerx04   01 ( default should read some thing like xxx0xxx1 , meaning PLL is enabled and hopefully it is locked ok)

W device_address registerx04  new_value    use a code exactly like what you read except LSB should change to 0 that is xxxxxxx0

r device_address  registerx04   01  hopefully now he reads xxxxxxx0 

On top of this test, he can write in to another register and then read it back to see it matches with what he  expects. 

I used a different  GUI (PUREPATH Consul) and I was able to write and read the same code back into Reg 04. So it is writing correctly for me. May be you can try to use a different GUI and see if it solves your problem?

We do not have any additional document beside what is mentioned in the product page. I believe datasheet is also the correct one and it was updated in 2016.

Regards,

Arash

Hi Arash,

Here is the feedback of our customer.

When I load : PCM5101_USB_Playback (no modifications) I can see that PLL is enable (register 04 by default). When I check (picture named : LRCLK_BCK_SCK):

TP13 : LRCK(Fs = 96 [KHz])

TP11 : BCK : 6.14 [MHz]

TP10 : 24.576 [MHz] = SCK because Register 13 is 000 (PLL reference clock is SCK).

It means that : Fs = (PLLCLK x K x R)/ (2048 x P) wih K = J.D

In the script it is written in comments :

# Set P=2, J=8, D=0
So : Fs = (24.576 [MHz] x 8.0 x 1)/ (2048 x 2) = 48 [KHz]

Question 1 : Am I wrong with my calculated Fs ?

By the way I send from Audacity a sinus of 1[KHz] with Fs = 48 [KHz].

As you can see in TP13 LRCK is not good so I'm interested to change this Fs. I would like to have 48 [KHz] of Fs from the PLL.

There is a picture of the evalboard as you can see I did not remove the jumpers. I guess it should be done but I don't see which one.

Question 2 : What should I do to have this Fs on TP13, what registers/jumpers I have to change ?

At the end I measure the THD and with this configuration the THD is not good at all.

Regards,

Danilo

Hello ,

I think his question regarding  reg 04 reading is resolved  and now he has a new question regarding coefficients of PLL.

Before anything ,please ask him to refer to table 33, note for fs=48k, BLK is 3.07MHz and for fs:96kHz BLK is 6.14MHz( which he is reporting correctly) 

Also Please ask him to refer to users guide  for jumpers set up  and follow that. 

the series of jumpers in the middle of the board connects the left side to right side , so the 3ed jumper from bottom, passes the signal on  TP28 (left)  to TP13( on the right).

if he is providing 48K using AP or Audacity , he should read it on TP28. Remove the middle jumper and measure it on TP28.  

Regarding his calculation, when PLL is enabled then

PLLCK = (PLLCLKIN × K × R) / P

So  for SCLK (PLLCLKin)  = 24.576 MHz  and   Fs*N= PLLCLK  ,  N should be chosen such that result  is within the range .

Also note 

• 64MHz ≤ (PLLCKIN x K x R / P ) ≤ 100MHz (in VREF mode)

• 72MHz ≤ (PLLCKIN x K x R / P ) ≤ 86MHz (in VCOM mode)

Regards,

Arash

Hi Arash,

Please see our customer's response below.

Thanks for your answer.

I understand better where my problem is, it is on the TP28 pin. When I send a 10 [KHz] sine with an Fs = 48 [KHz] 

here is what I read on TP27, 28 and 29 the frequencies respect Table 33.

I can read that on TP28 (the jumper in the middle has been removed) Fs = 44.1 [KHz] when it should be 48 [KHz]. I don't understand why I don't get the right Fs ?

I may have an idea about the origin of my problem, it may be due to the fact that in the windows settings of the sound the sampling frequency remains the same and that the DAC sets itself to this sampling frequency and not to the one of Audacity. But I can't change the sample rate unfortunately. You can see the setting in : USBAudio-EVM Settings.

Regards,

Danilo

Danilo, I get 48k on my system , it is grayed out and I can not change it.

Hi Arash,

I just received this update from our customer.

I have a question about PLL configuration. In the code "PCM5101_USB_Playback" there are 3 lines describing how to set up the PLL where p = 2 and K = 8 ( picture PLL_configuration).

Unfortunately these registers 0F, 10 ,11 (15,16,17) do not exist in the datasheet (picture : PLL_configuration_problem), why ?

Even if we start from the registers of the datasheet allowing to modify P, J , D etc... that is to say the registers in hexa : 14,15,17 (in decimal : 20,21,23) we never find these registers in the code (but it is specified by the comment: # Set P=2, J=8, D=0 that these parameters were configured).

So in which register can we modify them ?

Regards,

Danilo

Danilo,

referring to datasheet, registers 20,21 and 23 are the registers to set the PLL coefficients. This is also mentioned in Table 35. PLL Registers.

Regards,

Arash

Hi Arash, 

Good day. Thank you for your response. We received feedback from our customer. Please see below.

So last inquiry was about the configuration of the registers, now it's configured

Today I received access to PurePath Studio but I only worked with CodecControl.
However, I generated a code(code.txt attached)

This code is mixed I started from the "PCM5101_USB Playback" database and modified it

My problem is after I've run the code registers haven't changed as you can see

The code works (I mean he is sent to PCM5142) and at the output, I have a sinewave

When I read the data all registers I modified are the same why?

Like register 25 (Hexa) is the same

the problem is in my code there is something that I don't change

Just add that I'm not using Pureath only write in registers

Normally, it will work with only coding registers

I mean it's what I guess"

1563.Code.txt

# The following script is used for playback via USB 

# RESET RESET THIS IS MASTER RESET FOR SRC (48kHz)

# Page 0 = DEFAULT for Control

# Write to page 0
w E0 7F 00

# Register 01, Bit 7 = 1 resets to default
d 100
w E0 01 80

# Delay 0.1 sec to allow part to reset
d 100

# Systeme mode "StandbyMode"
w E0 02 01 
# Disable all clock missing detectors and clock auto mode
w E0 25 7F 

# Register 01, Bit 7 = 0 for normal operation
w E0 01 00
d 100

#----- Setup Port A ------#

# power on port A and B
w E0 01 38

# set up port A as master, 24 bit I2S sourced from port B
w E0 03 19 

# PLL enable 
w E0 04 01

# port B slave, 24 bit I2S
w E0 05 01 


#----- PLL Configuration -----#

# Registers configured by default cannot be written
w E0 0F 22
w E0 10 1B
w E0 11 A3

# PLLCK = CLKIN x R x (J.D) / P = 11.3MHz x 1 x 8 / 1 = 90.316 MHz
# PLL clock source = SCK
w E0 0D 00 
# P = 1
w E0 14 00 
# J = 8
w E0 15 08 
# Decimal value = 0
# R = 0
w E0 18 00 

#DSP CLK = PLLCLK/DDSP = 90.316 MHz /2 = 45.15 MHz
# division by 2
w E0 1B 01 
# DAC CLK = PLLCK/DDAC = 90.3168 / 16 = 5.6448MHz
# Division by 16
w E0 1C 0F 
# CP(charge pump) Clock = DAC CLK / NCP = 5.6448MHz / 4 = 1.4112MHz
# Division by  4
w E0 1D 03 
#  Oversampling Ratio clock = DAC CLK /DOSR = 5.64MHz / 8 = 705.6KHz
# Division by 8
w E0 1E 07 


#----- GPIO Configuration -----#
# GPIO1 Config
# GPIO1 = RCVR non-audio data
w E0 1B 06
# GPIO2 Config
# GPIO2 = RCVR non-valid data
w E0 1C 07

# Power Status
# Disable RCVR (/PDRX) and Port B(/PDPB) power down and enable All Function power down
#w E0 01 14

#w E0 03 29

MyCode.txt

# The following script is used for playback via USB 

# RESET RESET THIS IS MASTER RESET FOR SRC (48kHz)

# Page 0 = DEFAULT for Control

# Write to page 0
w E0 7F 00

# Register 01, Bit 7 = 1 resets to default
d 100
w E0 01 80

# Delay 0.1 sec to allow part to reset
d 100

# Systeme mode "StandbyMode"
w E0 02 01 
# Disable all clock missing detectors and clock auto mode
w E0 25 7F 

# Register 01, Bit 7 = 0 for normal operation
w E0 01 00
d 100

#----- Setup Port A ------#

# power on port A and B
w E0 01 38

# set up port A as master, 24 bit I2S sourced from port B
w E0 03 19 

# PLL enable 
w E0 04 01

# port B slave, 24 bit I2S
w E0 05 01 


#----- PLL Configuration -----#

# Registers configured by default cannot be written
w E0 0F 22
w E0 10 1B
w E0 11 A3

# PLLCK = CLKIN x R x (J.D) / P = 11.3MHz x 1 x 8 / 1 = 90.316 MHz
# PLL clock source = SCK
w E0 0D 00 
# P = 1
w E0 14 00 
# J = 8
w E0 15 08 
# Decimal value = 0
# R = 0
w E0 18 00 

#DSP CLK = PLLCLK/DDSP = 90.316 MHz /2 = 45.15 MHz
# division by 2
w E0 1B 01 
# DAC CLK = PLLCK/DDAC = 90.3168 / 16 = 5.6448MHz
# Division by 16
w E0 1C 0F 
# CP(charge pump) Clock = DAC CLK / NCP = 5.6448MHz / 4 = 1.4112MHz
# Division by  4
w E0 1D 03 
#  Oversampling Ratio clock = DAC CLK /DOSR = 5.64MHz / 8 = 705.6KHz
# Division by 8
w E0 1E 07 


#----- GPIO Configuration -----#
# GPIO1 Config
# GPIO1 = RCVR non-audio data
w E0 1B 06
# GPIO2 Config
# GPIO2 = RCVR non-valid data
w E0 1C 07

# Power Status
# Disable RCVR (/PDRX) and Port B(/PDPB) power down and enable All Function power down
#w E0 01 14

#w E0 03 29

Please help to advise. Thank you for extending your support.

Kind regards, 

Marvin

Hi Marvin,

I am in a summit today and will look at it on Monday.

Regards,

Arash

Marvin, 

would you please ask them to do a register dump to make sure the address of the device they are using  is what it is supposed to be ( For example if the address is 98 but they are using E0,  it  can not communicate with the IC).

I checked the register dump and the device address on the EVM  is set to 98, may be they are using the IC address for the PCM5101??

Regards,

Arash

Hi Arash, 

Thank you for your response. Please see the feedback from our customer.

I've seen something that can help experts.

When I use a code and run it with the device E0 I can read at the bottom of the window that: EVM Status Connected as you can see in the following picture.
Whereas if I use the same code but with device 98 I can read: communication error as you can see in the picture.
The device number used is the correct one, it would be interesting if the expert tried to run my code.

Please help to advise. Thank you for extending your support.

Kind regards, 

Marvin

Hi Marvin,

The correct GUI for PCM5142 is what I mentioned above,  which is also mentioned on TI webpage. This GUI  recognizes the part correctly and the device address for PCM5142 is 98 when I read the register dump.

We can not predict  what happens when we use a wrong gui with a different part's  script  (PCM5101) and   connect a different IC (PCM5142)  with different address. My guess is  that it sees the TAS1020 and confirms it is connected,  but it is not able to communicate with the chip because of the wrong address.

When I connect CodecControl to PCM5142 EVM, it doesn't recognize the EVM.

Regards,

Arash