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SRC4392: MCLK deviation tolerance

Floris S
Prodigy 10 points

Part Number: SRC4392

I was wondering how much (in ppm for example) the MCLK frequency is allowed to deviate from the value set in Register 11: PLL1 Configuration Register 3 when used as reference for DIR.

  • 0
    TI__Mastermind 32741 points

    Hello Floris,

     Data sheet doesn't have this kind of information and  I can not really give you a number for tolerance. All we can tell is for common reference clocks and  for various PLL coefficients,  it might have 0.0003 percent error and it is fine with this range of error.

    Regards,

    Arash

  • 0 in reply to Arash Loloee
    Prodigy 10 points

    Hi Arash,

    Thank you. So that would be 3ppm.  The crystals on the EVM are +/-50ppm.
    Since the specified tolerance of most crystals is something like 10-20ppm (or more) this would mean tuning or a strict pre-selection?

    With kind regards,

    Floris

  • 0 in reply to Floris S
    TI__Mastermind 32741 points

    Hi Floris,

    As i mentioned we do not have the information regarding tolerance  of MCLK and the 0.0003 percent  error mentioned was not meant to be used as a guideline or boundary.

    The only information that is in the datasheet regarding crystal oscillators selection is the following:

    It is recommended that the clock sources for MCLK and RXCKI input be generated by low-jitter crystal oscillators for optimal performance. In general, phase-locked loop (PLL) clock synthesizers should be avoided, unless they are designed and/or specified for low clock jitter.

    Regards,

    Arash