PCM1803A: No D out, need design review and guidance for debugging

shall respond tomorrow(04/05)

Can you connect OSR pin to 3.3v and see if any change happens.

Please semd me the waveform on pin 1 and 2 (Oscilloscope on DC Coupled mode)

Will get those changes made tongiht and let you know, I am putting in a * DTMF tone typically, but will get those waveforms captured (will be at C19 and C20 as the PCM1803A chip is burried under the USB card that produces the clocks)

ok

Changing OSR to 3V3 does not change anything, getting about 100mVdc mean, just getting noise signal

Clocks

Pin 10 = 47.998Khz (Square 50%)

pin 11 = 3.0719Mhz (Square 50%)

Pin 15 = 24.575Mhz (sine)

Confirmed

3v3 and 5V rails are at the right voltages,

5V rail takes ~1ms to rise, 

3v3 rail takes ~50uS to rise

5V rail turns on ~7ms prior to the 3V3 rail

Vref , Vref2, VINL, VINR  = 1.67Vdc

tone voltage is (VINL, pin 1) is approximately 350mVpp

brought out the !PDWN signal as well with a pull down so I could force reset the device, no change after reseting the chip, still no DOUT

Pin1 input directly at the chip pin shown above

Pin2 is the same as pin 1 

Is the yello waveform is riding on a DC of 1.65v?

Yes, see the top left measurement, Vavg = 1.66V so that is the DC component of the signal

sorry, top right measurement.....

There may be some kind of issue with the clocks. Where are the clocks coming from? An issue with the input timings might also result in no output.

one possible issue is mentioned below.

one way to try debug this is to set the chip in master mode . For this MODE1 should be connected to 3.3v and OSR should also be connected to 3.3v.  We can then give an input SCKI of 384*44.1Khz  or 16.93 Mhz from any signal generator snd see if BCK/LRCK and DATA start appearing.

Below are the timings mentioned in the datasheet,

If Master mode starts working then we are sure everything apart from timings is fine

The clocks are coming from a device called the USBSTEAMER (https://www.minidsp.com/products/usb-audio-interface/usbstreamer) which converts USB <-> I2S

I am not familiar with this device. Are LRCK and SCKI in Sync in this device?

perhaps if you try master mode in our chip and we start getting an output then at least we can conclude that Hardware connections are OK and there might be an issue with timing. 

I am not sure how to get this 16.93MHZ at the moment, It may take me a bit to locate a suitable clocking source

Clocks appear to be well syncronized with good amplitude, I do not see any jitter or alignment drift

1) I am able to get the mclk to 22.578Mhz by playing out a 44.1khz format, would this work?

2)

Should VREF2 be tied to +5V? I see this was done in the EVM schematics (I don't have an EVM, just reviewing the implementation)

I shall reply tomorrow.

Yes the 22.578 Mhz can be used as the clock source in master mode.

I have included a snapshot from PCM1801 datashet. The input circuits are familiar to this device . VREF1 and VREF2 are 

internally generated .The analog input pins are loced to this level and also should be same level as Vref

Connecting Vref to 5v would cutoff the input op amp. I think its fine leaving both Vref pins open and just connected a capacitor 

to ground.

However the snapshot below shows that the Vred1 value should be 0.5*Vcc=2.5v. I notice that your measurement shows

1.67 V., Are we sure that the 5V is reaching the Vcc pin of the IC? Please check direct on the pin.Also is there a chance that this chip might be faulty?

I will confirm at the pin level on the 5V supply, also I am expecting delivery of the EVM today so I can hook my clocks up to that board as well to confirm if it behaves the same

OK . ts good to check with an EVM