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SRC4190: About reset time

Youhei Miyaoka
Intellectual 2365 points
Part Number: SRC4190
Other Parts Discussed in Thread: SRC4192

Hi, experts

My customer have some question about SRC.

Can you please confirm the following for RST on 13PIN?
- What is the state of each port when RST is low?

- How long does it take the recovery time when RST signal is low to high?

Thank you

Youhei MIYAOKA

  • +1
    TI__Mastermind 23960 points

    The  RST pin is used to initialize the internal logic at any time. The reset sequence forces all registers and buffers to their default settings. The reset
    low pulse width must be a minimum of 500ns in length. Upon reset initialization, all functional blocks will default to the powered-down state, with the
    exception of the SPI or I2C host interface. The user can then program the SRC4192 to the desired configuration,

    You need a min of 500us before you do another Write or Read via SPI or IC.

    Regards,

    Arash

  • 0 in reply to Arash Loloee
    TI__Intellectual 2365 points

    Hi Arash,

    Thank you for your answer.

    My customer has a question about the powered-down status during reset.

    What is the specific state of each pin in the power-down status.

    It would be helpful to answer each pin number and state (High-z, Low, High).

    Specifically, the pin names and numbers shown below.

    CK I/O (5,6,24,25)

    BYPAS (9)

    IFMT (10,11,12)

    LGRP (1)

    MODE (26,27,28)

    MUTE (14)

    OFMT (18,19)

    OWL (16,17)

    RCKI (2)

    TDMI (20)

    SDI/O (4,23)

    RDY (15)

    VIO, VDD (7,22)

    GND (8,21)

    Regards, 

    Youhei

  • 0 in reply to Youhei Miyaoka
    TI__Mastermind 23960 points

    Hello,

    please note that when you power down a chip , in general,  you are not changing the status of the input pins and supplies: if you are applying some digital signals to digital pins or applying analog inputs to analog pins,  supplies and GND ,  they will not change. Only the output pins will be effected by the PD.

    Here for example,  outputs such as SDout or CLKO  will halt or go low;  similarly  RDYZ signal ( which is an output pin) will show the chip is not ready and will go High.

    Your supply pins and GND will still read the same voltage. if you had put Hi ( for example)  on OFMT pin ( input) still it will read Hi. 

    Regards,

    Arash

  • 0 in reply to Arash Loloee
    TI__Intellectual 2365 points

    Thanks Arash,

    I hope you had a great weekend!

     

    I have 2 points that I need to make sure.

    You said, "outputs such as SDout or CLKO will halt or go low".

    1. Halt means that pin status will go high-z?
    2. SDOUT pin will halt and CLKO pin will go low, is it correct interpretation ?

     

    Regards,

  • 0 in reply to Youhei Miyaoka
    TI__Mastermind 23960 points

    Hello, thanks for your comment.

    By halt I mean it will stop toggling. While it depends on the design, in most cases once a signal stops toggling it goes low.  For example SDOUT will go low with no activity. Usually  data sheet tells you a signal would go to High-Z   if that is the case.

    Regards,

    Arash