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PCM1803A: power down mode

Yasushi Fujiwara
Genius 12535 points
Part Number: PCM1803A

Hello Experts,

My customer has question as follows. Would you answer it, please?
1. When /PDWN is toggled L to H, how much time is need to output from DOUT?
2. While device is power down mode and clocks are input, customer would like to know power dissipation of Icc and Idd. The datasheet stated only clock halt.

Best Regards,
Fujiwara

  • 0
    TI__Expert 6325 points

    Hello Yasushi, 

    1. According to the datasheet in section 7.3.2: Power-On-Reset Sequence, "The PCM1803A has an internal power-on-reset circuit, and initialization (reset) is performed automatically at the time when power-supply voltage (VDD) exceeds 2.2 V (typical)"

    2.And the power dissipation in power down mode is 28uW with clock test conditions: fS = 44.1 kHz, & system clock = 384 fS in section 6.5: electrical characteristics. 

    I hope this was able to answer your question.

     

    Best regards,

    Ore. 

  • 0 in reply to Ore Ogundana
    TI__Genius 12535 points

    Hello Ore,

    Regarding question #1, you mean that the time is "1024 System Clocks + 4480 / fs", correct?

    Regarding question #2, you showed table is clock halt condition, I think. Please confirm below comment.
    "(8) Halt SCKI, BCK, LRCK"

    Best Regards,
    Fujiwara

  • 0 in reply to Yasushi Fujiwara
    TI__Expert 6325 points

    Hello Yasushi, 

    1. Once VDD > 2.2V, 1024 system clock cycles( 256 fS, 384 fS, 512 fS, or 768 fS) and a time period of 4480/fS need to elapse to get any data out. You can apply T=1/1024(XfS) + 1/(4480/fS) to determine how much time you would need to get data out. So yes your calculation is correct.
    2. Yes, in power down mode, Icc and Idd are 5uA and 1uA respectively when clocks are halted. To find out Icc &Idd power dissipation when clocks are not halted, please allow me some time to test this theory and get back to you with an update on or before end of day Tuesday.

    Best Regards, 

    Ore. 

  • 0 in reply to Ore Ogundana
    TI__Genius 12535 points

    Hello Ore,

    OK, please take a look at power dissipation while clks are not halted in power down mode.

    Best Regards,
    Fujiwara

  • 0 in reply to Yasushi Fujiwara
    TI__Expert 6325 points

    No problem.

    BR,

    Ore.

  • 0 in reply to Yasushi Fujiwara
    TI__Expert 6325 points

    Hey Yasushi, 

    I'll like to extend giving you an update till the end of the week. Thank you for your patience. 

    Regards, 

    Ore.

  • 0 in reply to Ore Ogundana
    TI__Genius 12535 points

    Hi Ore,

    Would you provide a test results for power consumption in power down mode(clks are not halted), please? It already delayed 10 days...

    Best Regards,
    Fujiwara

  • 0 in reply to Yasushi Fujiwara
    TI__Expert 6325 points

    Hello Fujiwara, 

    I am trying to investigate the results for the Icc, Idd and power dissipation using the power-down mode with the clocks not halted. I would like to point out the datasheet states Icc and Idd specs separately and not the power dissipation at Icc or Idd. Since this is not in the datasheet, allow me till the end of the week to test this.

    Best regards, 

    Ore.

  • 0 in reply to Ore Ogundana
    TI__Expert 6325 points

    Hey Fujiwara, 

    Maintaining the same test conditions as the datasheet showcasing the Idd, Icc and power consumption in power down mode. All those parameters remain close to the same when the clocks are on or off with the ADC in master mode. 

    I hope this answered your question. 

    Best regard,

    Ore. 

    This thread was moved to email, so I would be closing this thread.