TAS2564: Is there a conflict between td(DO-SBCLK) with a maximum of 21ns and SBCLK with a maximum of 24.57Mhz?

Hi Amy,

I'll take a look at your questions and provide some feedback by tomorrow before the end of the day.

Best regards,
-Ivan Saazar
Appliations Engineer

Hi Ivan,

Sorry for the delay. 

Thanks for your support.  

Hi Ivan,

Our customer needs to know the minimum value of td(DO-SBCLK) to ensure that the hold time of the data meets the requirements. Could you please help find and confirm this minimum value?

Best Regards,

Amy

Hi Amy,

Today is a TI US holiday, and Ivan was travelling last week. He will get back to you on Tuesday.

Thank you for your patience,
Jeff McPherson

Hi Amy,

I may not be clear on what's the difference between this last question and the previous one. td(DO-SBCLK) only has max spec. Please notice SDOUT is the data coming out of TAS2564 meaning it depends on the TAS2564 itself, whereas SDIN is the data coming into TAS2564 so its timing must be controlled by the host device.

Best regards,
-Ivan Saazar
Appliations Engineer

Hi Ivan,

Sorry for the late response.

The customer is concerned that the difference in td (DO SBCLK) parameter values between different batches of TAS2564 may cause problems. For example, if the program uses DOUT to emit on the rising edge of SBCLK, and if the td (DO SBCLK) of the next batch of devices is the minimum value, then it depends on whether the minimum value of td (DO SBCLK) can meet the master's hold time.

Best,

Amy

Hi Amy,

Sorry for the confusion, but I still don't understand the concern. Is the concern that the hold time cannot be long enough?
Perhaps creating a new timing diagram with the concerning case may help us understand? We can also have a call to discuss this further if required.

Best regards,
-Ivan Salazar
Applications Engineer

Hi Ivan,

Yes, the customer is concerned that the hold time may not be long enough for the following situations

Ivan Salazar said:

if the data is sampled on the falling edge of SBCLK, the delay time is from the last SBCLK falling edge to the next sample of SDOUT, meaning you actually have 40ns - 21ns = 19ns to setup the next SDOUT sample.

The above situation you described assumes that SBCLK to SDOUT delay is 21ns. At this point, there is no problem with setup time and hold time. But if the td (DO-SBCLK) value of TAS2564 in the next batch is the minimum value, such as 0ns, then in this case, the holding time is not long enough. So, customers need to know the minimum value of td (DO-SBCLK).

Hi Amy,

So the concern is that if td(DO-SBCLK) is 0, the device would not be able to hold the SDOUT pin for the whole 40ns? Why would that happen?
If a diagram could explain better, please share.

Best regards,
-Ivan Salazar
Applications Engineer

Hi Ivan,

Could you provide or find the minimum value for td(DO-SBCLK)? Now the customer doesn't want to explain why they need its minimum value, they just need us to provide it to them.

Thanks,

Amy

Hi Ivan,

Thank you for your response. This user ultimately provided a diagram, as shown in the attached figure:

Please ignore the BCLK and BCLK_inv signals in the diagram.

The user's situation is that their main control end can only sample at the rising edge of SBCLK. We know that TAS2564 can be set to transmit DOUT data on the falling or rising edge of SBCLK.

Requirements for the main control end: t_ Setup>6ns, t_ Setup>4ns,BCLK=24.576M

The situation that users are concerned about is:

When setting TAS2564 to transmit DOUT data on the falling edge, if the td (DO-SBCLK) value of TAS2564 used is 21ns, there cannot be a setup time of 6ns.

Or when setting TAS2564 to transmit DOUT data on the rising edge, if the td (DO-SBCLK) value of the TAS2564 used is 0ns, there cannot be a hold time of 4ns.

Because different TAS2564 have different td (DO_SBCLK) values, in the most extreme cases, some TAS2564 have a td (DO SBCLK) value of 0ns, while others have a td (DO_SBCLK) value of 21ns. And TX_ EDGE can only configure one situation where the software cannot adapt to both situations simultaneously. Because whether using the rising edge to transmit data or the falling edge to transmit data, both the setup time and hold time cannot be met simultaneously.

Best Regards,

Amy

Hi Amy,

I'll discuss these questions with some of my colleagues to get a fresh view so we can better understand the concern from customer side.
I'll get back to you by mid of the week.

Best regards,
-Ivan Salazar
Applications Engineer

Hi Ivan,

Sorry for pushed, any update on here?

Hi Amy,

After reviewing I have further comments below:

• Perhaps customer specs for setup and hold times, are referred to digital data output from SoC to TAS2564, meaning SDIN from TAS2564 perspective. There are similar setup and hold times called for SDIN in TAS2564 data sheet, and both are higher than 6 and 4 ns respectively.
• td (DO-SBCLK) spec is the time after the sampling edge until the next SDOUT transition. As long as SDOUT is properly latched during the selected SBCLK edge, the delay from the end of that edge to the next transition on SDOUT can take as much as 21ns, but there is no minimum because the data is already latched. This is the reason why no minimum is specified in this case.

Hope this helps close this question, let us know otherwise.

Best regards,
-Ivan Salazar
Applications Engineer