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TLV320ADC5140: PDM 16,000 Sampling Supported?

Chris Nielsen
Intellectual 615 points

Part Number: TLV320ADC5140
Other Parts Discussed in Thread: PCMD3140

I can't find it mentioned in the datasheet, but I'm assuming that the PDM decimation rate is the rather standard 64X, right?  SBAA381 talks to 16K sampling, but is this only for analog?  The DS 7.3.5 concerns me in that it states only certain clocks supported...if I use 64X, then it appears 16K is not supported, right?  If 16K is out, 48,000 is available with 3.072M/64, right?  Thanks, Chris

  • 0 in reply to Sanjay Dixit
    Intellectual 615 points

    Sounds good.  Related question.  I can't find answer in DS.  Will audio be degraded (SNR, DR, effective bits, etc) if I set PDM clock for 16K vs 48K?

  • 0 in reply to Chris Nielsen
    TI__Mastermind 23030 points

    I pick a selection from SBAA493 

     

    This indicates that if Fsync is a Multiple or submultiple of 48K , we can create a PDM clock of 6.144Mhz/3.072Mhz/1.536Mhz/768K by making an appropriate selection in PDMCLK_CFG Register.

    I now refer to the datasheet of PCMD3140. This device has an identical functionality for Digital Mic as the ADC5140. At one place it describes the SNR and the dynamic Range at Fs=48k,BCK=256Fs and PDM CLK of 3.072Mhz. A dynamic Range of 130 db is seen which is more then any Digital Microphone.

    Looking at this I suggest this setting . With other combinations its possiblethe PLL conditions are different and might provide more jitter leading to a poorer noise floor.