I see a dB Dynamic Range (DR) progression in the TI Audio ADC product line:
PCMD3140 4th-order=117 (19.43 bits bits) 5th-order=127 (21.09 bits)
ADC6140 4th-order(?)=113 (18.77 bits)
ADC5140 4th-order(?)=108 (17.94 bits)
ADC3140 4th-order(/)=106 (17.61 bits)
This implies that for a given PDM mic, if more silicon is applied, we can reach a higher effective number of bits, right?
For the ADCX140 series, it's never stated, but does the part rely on 4th-order PDM mics? Will it work with 5th-order? Tradeoffs? Seems like a great place for an app note to help application folks to understand the tradeoffs and select a proper set of parts without overdesigning...
Our application is far-field, low signal, hence the interest in saving the weak bits at the low end of the ADC. Or, put another way, if we have a PDM mic with 26 dBA of self-Noise (68 dB SNR), it would be silly to digitize too far below that noise floor, and that is where I get a bit confused on the math at the system level.
Thanks, Chris
