TAS6424E-Q1: How to understand tSF and tFS

liujian zhang

Prodigy 230 points

Part Number: TAS6424E-Q1

How to understand tSF and tFS, would you pls give an example, thanks!

would you pls help give an actual example(what's the actual points on waveform, ) for these parameter, thanks!

over 2 years ago

0 Gregg Scott over 2 years ago

TI__Mastermind 44955 points

Please see the description and specification on page 11 of the datasheet.

Regards,
Gregg Scott

0 liujian zhang over 2 years ago in reply to Gregg Scott

Prodigy 230 points

Hello, pls help to give a illustration, thanks! also, pls help to check below waveform is right or not?

tFS:

tSF:

0 Shadow He over 2 years ago in reply to liujian zhang

TI__Mastermind 49360 points

Hi Liujian

Your waveform seems no problem. The key to this two parameter, is to change the LRCLK level at the point of falling edge of SCLK, which is the most standard using. Using this way, you needn't to worry about this two parameter any more.

0 liujian zhang over 2 years ago in reply to Shadow He

Prodigy 230 points

Hello Shadow,

thanks for you reply! but still not understand very clearly, "LRCLK" means "FSYNC"? you mean "FSYNC" level change(low-->high or high-->low) should at the point of falling edge of SCLK, right?

how to understand 8ns? thanks!

0 Shadow He over 2 years ago in reply to liujian zhang

TI__Mastermind 49360 points

Hi Liujian

liujian zhang said:
LRCLK" means "FSYNC"?

Yes, FSYNC and LRCLK are the same things, it has different name from different literature.

liujian zhang said:
FSYNC" level change(low-->high or high-->low) should at the point of falling edge of SCLK, right?

Yes, that is the standard using.

liujian zhang said:
how to understand 8ns?

That is the minimum time digital side used to guarantee clock safety. The rising edge is the effective point in SCLK, when FSYNC need to change, the flip position need to be far away from the rising edge of SCLK.

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TAS6424E-Q1: How to understand tSF and tFS