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TAS6584-Q1: Information Needed

Renan Santos Adriano
Mastermind 23310 points
Part Number: TAS6584-Q1


Hello Team,

Posting on behalf of my customer:

1. It says it can be configured to drive four channels of BTL outputs with ample power (e.g, 75W x 4 into 4 ohms) at the higher voltage range like 24-36V?  Can we verify those specifications?
2. What is quiescent draw at higher voltage rails like 24V?
3. Can we get schematics, BOMs, layout files for the EVM board

Regards,

Renan

  • 0
    TI__Mastermind 19880 points

    Hi Renan,

    1. Yes, you can refer  to Figure 6-13. Output Power vs Supply Voltage in datasheet.

    2. Please refer to Figure 6-32 and Figure 6-33 PVDD/VBAT Idle Current vs Voltage.

    3. Please send e-mail to us, we can share to you.

    Regards,

    Derek

  • 0 in reply to Yanming Gong
    TI__Mastermind 23310 points

    Hello Derek,

    Good day. Please see response from my customer:

    I just received the secure links and download the data sheets and EVM design files for the TAS6584. Unfortunately, the design files for the EVM were not what I was asking for. While the gerber, pdfs, and BOM Excel files are helpful, I was asking for the Altium SOURCE files for the Project, Schematic, and PCB. These would be native Altium files not just pdf and gerbers. I have asked and received these files for other EVMs you make.

    Also, I want to make sure I understand the best way to use this part for our application. We intend to use it in various applications where the power supply can range for 9V to 30VDC with the most common uses at 24VDC. The datasheet seems to indicate that you can connect VBAT to PVDD and the total idle current at that voltage will be around 20ma (PVdd) + 80ma (VBAT) = 100ma total. Is this correct? Also, our PVDD/VABT would come up together and the 3.3V for the logic would likely come up shortly after with the opposite happening on power down. Any issues with that? Lastly, where and how can I purchase an EVM board for this part?

    I want to add to my last post that someone in the forum sited high-power consumption in sleep mode when Vbat was connected to PVdd and power significantly reduced when he connected VBAT to a lower voltage. I'd like not to have to introduce a separate regulator for VBAT (since my input power range voltage is so wide). Please advise your recommendations.

    Regards,

    Renan

  • 0 in reply to Renan Santos Adriano
    TI__Guru 51860 points

    Hi Renan

        I'll send you the EVM project through e-mail. To apply for EVM, please e-mail to our Marketing John (j-satterla@ti.com). 

        By connecting PVDD and VBAT together, there would be much larger power loss created, you'll need to handle the power dissipation. 

    Renan Santos Adriano said:
    the total idle current at that voltage will be around 20ma (PVdd) + 80ma (VBAT) = 100ma total.

    The datasheet says 120mA at 480KHz PWM and under 14.4V.

    Renan Santos Adriano said:
    and the 3.3V for the logic would likely come up shortly after with the opposite happening on power down. Any issues with that?

    The most important thing is to pull down STBY pin before any power supply drops, as datasheet requires below: