Hi ti Team,
Please check if there is any problem with the schematic diagram below?
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Hi ti Team,
Please check if there is any problem with the schematic diagram below?
Hello,
I will take a look at the schematic and let you know by the end of Wednesday as we are approaching a holiday.
Regards,
Arash
Hello, I reviewed the DIT4096 portion of the schematics and I have the following comments/observation
CLK0 and CLK1 are Master Clock Rate Selection (TABLE II) . I don't see where 4096_CLK1 is connected to. Should not be floating.
Mono is set to 0 ( meaning it is stereo) but only TX+ is used, maybe I am missing something here.
Based on FMT pins ., 24-Bit Left-Justified is selected, is it what they want? please refer to TABLE V. Audio Data Format Selection for Hardware Mode.
Other than that it looked okay to me.
Kind regards,
Arash