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PCM5121: low latency 3.5/fs vs 1.2/fs

Anderson Cheng
Intellectual 1240 points
Part Number: PCM5121

Hi Team,

when I test the PCM5121EVM the delay time is not match with the datasheet descprition.

in datasheet the 0x02 preset flow delay time is 3.5/fs, when fs=48K, but the AP actual test DUT delay time result is 104.3us.

the 0x07 preset flow is 1.2/fs, when fs=48K, but the AP actual test result is 125.0us.

question:

1.  what is the shortest delay time of the PCM5121?

2. why the 0x07 preset flow delay time is larger than 0x02 preset flow, why the delay result it not match with 3.5/fs or 1.2/fs.

Thanks.

Anderson

  • 0
    TI__Guru** 108395 points

    Hi Anderson,

    There may be a confusion on the settings for Page 0 Register 43, here some details:

    • There are 4 different filter settings for the interpolation filter, below is a capture of the different mentions of these in the data sheet:
    • The lowest filter group delay is the Asymmetric FIR, which configuration is 00111 on Page 0 Register 43 bits 4:0.
    • Notice this is the delay of the interpolation filter itself, other processing blocks would add to this.

    Best regards,
    -Ivan Salazar
    Applications Engineer

  • 0 in reply to Ivan Salazar
    TI__Intellectual 1240 points

    Hi Ivan,

    my test result turn out very strange result,the  Asymmetric FIR(0x07) is not the lowest delay about 125us. while the low latency flow(0x02) is the lowest delay about 104us.

    can you help to confirm if the test result is correct? below is my configuration setup:

    w 98 00 00
    w 98 01 11
    d 05
    w 98 2B 07
    w 98 0D 10
    w 98 25 0C
    w 98 3D 30
    w 98 3E 30
    w 98 41 00
    w 98 3F BF
    w 98 40 B0
    w 98 28 03
    w 98 02 00

    only changing the 0x2B register value from 0x02 to 0x07 for delay time test, other register setting remain the same.

    Thanks.

    Anderson

  • 0 in reply to Anderson Cheng
    TI__Guru** 108395 points

    Hi Anderson,

    I'll try to get the test setup on my side as well to double check. Should get back with further comments over the next week.

    Best regards,
    -Ivan Salazar
    Applications Engineer

  • 0 in reply to Ivan Salazar
    TI__Guru** 108395 points

    Hi Anderson,

    Not sure if you're still looking into this, but I could confirm the 125us as the lowest DUT delay measured on the device.
    I'll start an internal discussion to better understand the specified delay times from data sheet.

    Best regards,
    -Ivan Salazar
    Applications Engineer

  • 0 in reply to Ivan Salazar
    TI__Intellectual 1240 points

    Hi Ivan,

    yes, we would like to know what cause the 125us delay and whether it can be reduced.

    Thanks.

    Anderson

  • 0 in reply to Anderson Cheng
    TI__Guru** 108395 points

    Hi Anderson,

    I'm reaching out to our systems/design team to fetch for more information. It may take some time to dig for it, I'll keep you posted on the progress.

    Best regards,
    -Ivan Salazar
    Applications Engineer