PCM1840: PLL function

Hello Mochizuki,

Thanks for your question and I would like to clarify your question:

• You have a device with a BCK pulse of 37ns that you want to use with the pcm1840 that has a BCK pulse of 18ns, correct?
• And you want to find a way to synchronize the two BCKs, corrects?

Regards,

Ore.                             

Hi Ore,

A BCK is 48KHz x32BCK=1.536MHz,  Tbck=651ns.

However as I attached capture image, around every 1sec period 614ns once cycle BCK is appeared. This BCK cycle is 37ns shorter than 1.536MHz.

By this one cycle BCK frequency shift, it seems PCM1840 PLL could not make lock status. That is caused by BT module BCK behavior but we want to run ADC by using this BCK output.

PCM1821 PLL can be worked on this condition? 

Regards,

Mochizuki

Understood,

• So the BT module has a BCK that is 614ns in its last cycle and you want to use it with the pcm1840? Just so you know, the pcm1840 clocks would need to be synchronized with external clock lines to operate properly 
• And I would need to confirm if the pcm1840 and pcm1821 share the same PLL to determine the state of its operation by the end of the week.

For the pcm1840, I would suggest, configuring the BCK line and Data line to see if you can get better synchronization. The i2s data is latched to the falling edge of the BCK, maybe you can get your device to latch data to different bit clock edges:                                                                                                                                                                                                 

 And take this footnote into consideration:                                                                                     

Regards, 

Ore.

Hello Ore,

Thank you for your suggestion.

For your reference, we also had validated function of DAC side PLL with this strange BCK input from BT module.

PCM5102A internal PLL worked well without any noisy audio output, it is candidate for mass production socket.

However TLV320DAC3203 audio output level is changing every 1sec duration which is synchronized with shorter BCK clock cycle.   

This case may be I2S data latch makes malfunction.

Then this time PCM1840 PLL doesn’t work at all, in the case of slave mode ADC function, I expect SDOUT should not be Hi-Z even I2S BCK timing is not suitable.    

We are waiting your PCM1821's information.

Regards,

Mochizuki

Hey Mochi,

i have an update:

• The PLL information is not something we can share on the e2e platform. Please share more information of your application for us to consider sharing that piece of information with you. Maybe this support can be taken a step further as synchronization is a recommended for any clock features.  

Regards,

Ore.