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TLV320ADC5140: Cannot seem to get a SDOUT stream coming out even though FS & BCLK look correct

Part Number: TLV320ADC5140


I am not sure why this isn't working, but I've checked my settings multiple times and I've looked at the signal with a scope.

The output from the Jetson Nano I am using as a master shows 48kHz FS and BCLK 6.144Mhz, both VERY stable

I turn the ALSA driver on so I can watch the signals coming out, and then I also check the status registers as its supposed to be streaming

I am asking for TDM, 32-bit, 4 channel

ASI_STS keeps changed from 0x46 to 0x36 to 0xf6.  6 = correct for second part, I do not understand why it's having trouble locking on to the signal.

IT_LTCH0 shows as c0 which indicates both interrupt are being tripped for bad combination of FS and BCLK

DEV_STS0 = 0x0 , so it shut all the channels off

DEV_STS1 =0xc0, indicates all powered down.

I tried telling it to ignore the errors, but the output still does not change on SDOUT

The other odd thing is I have to write the wake up twice.  If I write it once and wait 1ms then continue, it doesn't seem to work.  But if I call twice, and recheck all registers, they are all correct

// Wake up device
spiADC(FD_AUD,0x02,0x81,0); //0 for last element indicates write
spiADC(FD_AUD,0x02,0x81,0);
std::this_thread::sleep_for(std::chrono::milliseconds(10));
printf("A Check Sleep Mode: %x\n",spiADC(FD_AUD,0x02,0x00,1));
// TDM & 32-bit (I2S only supports 2 channels, need TDM which supports 4) Also BCLK needs to be inverted
spiADC(FD_AUD,0x07,0x34,0);
// Let's turn off bus error detection
//spiADC(FD_AUD,0x09,0x20,0);
// 0x13 we leave default, sets in slave mode
// Setup line inputs for all 4 channels
spiADC(FD_AUD, 0x3C, 0xF0,0);
spiADC(FD_AUD, 0x41, 0xF0,0);
spiADC(FD_AUD, 0x46, 0xF0,0);
spiADC(FD_AUD, 0x4B, 0xF0,0);
// Enable all 4 ADC
spiADC(FD_AUD,0x73,0xF0,0);
// Enable ASI 4 output slots
spiADC(FD_AUD,0x74,0xF0,0);
// Power up ADC and PLL (not sure if these are right)
spiADC(FD_AUD,0x75,0x60,0);

Then from here it is calling ALSA driver.

 

  • I believe I should not be inverting the BCLK inside the tlv320adv5140 as further investigation, this BCLK configuration puts the rising edge 1/2 cycle ahead which passes the 9ns setup requirement.

    Still unsure why the detection mechanism internally is jumping around so much.  

    I checked all the power coming in, everything looks fine.

  • I went back and changed register 0x07 to 0x30 so the polarity is now correct and reran.  This resolved getting 0x36 from the detected settings in register 0x15, however, it didn't resolve all bad detections.

    My code runs a while loop while the interface is active and all it is doing is reading the status registers. 

     ASTI_STS STATS: 0x46 (3635) 0xf6 (1072)
     INT_LTCH0 -> c0
     DEV_STS0  -> 0
     DEV_STS1  -> c0

    I ran it for awhile and collected every single output that came from the ASTI_STS register.  You can see 0x46 which is correct happens 77% of the time.  This ratio appears to hold true.  The multiplier value (6) always remains correct.

    As I mentioned before, the signals on the scope are VERY stable.  I've tried various lengths of FCLK duty cycle with no difference.

  • Since I know this question will be asked next, here is the schematic of how I have hooked up the ADC.  Note I don't have any of the 4 single ended circuitry shown which is off screen.

  • Thanks for questions. Expect a response in 48 business hours. 

    Regards

    Ore.

  • I have discovered the problem, I replaced the IC on the board and I now see SDOUT streaming and the detection is working.