TLV320AIC3100: only a square wave in the output of the analog audio

for this feedback loop code 

u8 pucRegData[] = {
0, 0,
1, 128,
108, 1 ,
};

I would expect the input conneted to the output , and in the input is a 1k sin wave and in the output I see the same square wave. 

Hi Maikon,

LOP and LOM are not pin names for this part. Can you clarify if you are measuring a SPKx output or HPx output?

Also I do not understand the code segment you shared. Are you playing an analog sine wave to the ADC input and then looping that back through the DAC?

Thank you,
Jeff McPherson

hi,

the part is TLV320AIC3104, and the code I shared was the minimal registers setup for connecting the input MIC1LP to LEFT_LOM.

Sorry my mistake with the part number.

Hi Maikon,

Thank you for the clarification. Am I correct in reading your code as 

u8 pucRegData[] = {

[address],[data]
0, 0,
1, 128,
108, 1 ,
};

Also is your square wave the same frequency as your input? Does the square wave change if you decrease the amplitude of the input sine wave?

Thank you,
Jeff McPherson

hi Jeff, tks for your reply, I will try to check it but it means that a square wave is expected then even the input being a sine wave, when the bypass is set ? (and yes it is address and data).

Hi Maikon,

In general, no this is not expected. Can you clarify what bypass you are referring to?

Thank you,
Jeff McPherson

the register 108 can connect the input LINE1XX to the output LEFT_ or RIGHT_ . 

Hi Maikon,

Thank you for the clarification. While you test with lower signal level as before, I'll check on my end to see if I can recreate the effect or workaround it.

Best regards,
Jeff McPherson

that would be great !

just to know what to expect when working with the Passive Analog Signal Bypass mode, I would expect the input being linked to the output as a first test of the AIC3104

Hi Maikon,

I made a quick script that configures the analog bypass on the IN1L terminals. I checked it on the EVM and got good results. Let me know if you get any better results. 

w 30 01 80
w 30 07 80
w 30 6C 02
w 30 6C 03

Best regards,
Jeff McPherson

very nice ! now I have a reference. 

Just to confirm, are you providing any clock to TLV like MCLK ? if yes what is it ? (I understood for this by pass wont be needed but just to confirm.)

In my case I was setting to work with 48k for fs and MCLK is 12.288 MHz. 

Hi Maikon,

I went back and double checked. I was not providing an MCLK because I was running in slave mode. Section 10.3.3.1 has a note that in the absence of MCLK, BLCK can be used. 256fs = 12.288MHz is very typical.

Best regards,
Jeff McPherson

tks Jeff,

I understood that for this test we dont need any clock because we are basically connecting input to output. That`s why you did not have to provide MCLK or BCLK, please correct me if I am wrong. I am using this work as reference here and at this stage no clock being provided, and my TLV is also in slave mode. 

Hi Maikon,

The EVM I'm working with was providing a BCLK by default, but you are correct that it wouldn't have been necessary.

Best regards,
Jeff McPherson

Tks again for your help, I was able to set the feedback loop or by pass mode after some probing. Now I am trying to use the I2S interface, working with AIC3104 in slave mode, 48 kps as fs, also using CLKDIV_CLKIN, MCLK, Q=2, since my MCLK is 12.288 MHz of MCLK. Also my design is using only MIC1LP and MIC1LM and LEFT_LOM and LEFT_LOP, which worked with the pass by. Also I am focused now on the transmit / playback only, 

I am based on this diagrams plus datasheet:

reg , value 

1, 0x80,
3, 1<<4,
7, 1<<3,
8, 1<<2,
15, 33,
19, 1<<2 | 1<<7,
37, 1<<7,
41, 1<<6,
43, 0x0,
86, 99,
101, 1,

Hi Maikon,

Glad to hear the bypass is working. For you I2S set up I'm not sure what the ask is here? Are you running into a problem getting the playback path to work?

Thank you,
Jeff McPherson

omg yes ! 

I am trying to get some I2S data transmitted from my FPGA application to the output of the TLV. 

Hi Maikon,

Understood. I am out of office right now as it is a U.S. holiday but when I am back in the lab I can pull an example script for you to try that will enable the playback path.

Best regards,
Jeff McPherson

tks again, after some debugging I noticed some issues with my MCLK, once I fixed it and it was present in the interface, I started having response from the AIC3104 via I2S. 

Hi Maikon,

Great news. Are there any other pending issues you're having?

Best regards,
Jeff McPherson

for the playback mode , like in the figure I sent to you on the top of this thread,  I am only transmitting data to the AIC3104 via I2S, single endded, and only playback, these are the registers that I am setting:

0, 0, // select page zero
1, 1<<7, //software reset
7, 1<<3, //Left-DAC data path plays left channel input data
41, 1<<6, //DAC_L3 BUT COULD BE L1 for setting to the Volume control
37, 1<<7, //DAC power up left only
43, 0 , //left DAC is not muted and no gain
86, 9, //power up left line out, set gain to 0dB
101, 1, // CODEC_CLKIN uses CLKDIV_OUT

my MCLK is 12.288 MHz , and AIC3104 in slave mode,

can you confirm this ?

I'm not familiar with the code format you're using. What is the meaning of << ?

Thanks,
Jeff McPherson

1<<6 is six bit to 1 

41, 1<<6 means register 41  the 6th bit is set to 1

Hi Maikon,

It looks okay to me, but incase you run into any problems, I'm also attaching the Playback to Line Out script from the EVM GUI.

w 30 07 8A
w 30 66 A0
w 30 25 C0
w 30 29 02
w 30 2B 00
w 30 52 80
w 30 5C 80
w 30 4B 80
w 30 4E 80
w 30 56 09
w 30 5D 09
w 30 4F 09

It's a little more comprehensive and known to work.

Best regards,
Jeff McPherson

tks jeff,

can you do the test of this path ?

I am using these registers

0, 0,                                       // select page zero
1, 128,                                //software reset
15, 127,                                //PGA is not muted
81, 128 ,                              //PGA_L to LEFT_LOP/M and HIGH GAIN
86, 153,                                  // LEFT_LOP/M unmute, power up, output level control = 0db
101, 1,                                // CODEC_CLKIN uses CLKDIV_OUT

for me this is another passing by more but with some gain from PGA and left

Hi Maikon,

When I ran your script it didn't work. I believe you didn't have the PGA_L to LEFT_LOP set correctly. 128 = 0x7f, so you had max gain but the MSB sets the connection which is 0. I tweaked your script (see below) and made sure it worked. I set the gain back to default since I was clipping badly, but you should be able to make adjustments from here.

w 30 01 80
w 30 07 80
w 30 56 99
w 30 65 01
w 30 0F 00
w 30 10 00
w 30 13 40
w 30 15 40
w 30 51 80

Best regards,
Jeff McPherson

shame on me about the PGA_L, but I tested your script and worked !

Thank u !  then I calibrated for my needs in terms of PGA gain.

Hi Jeff , tks again for your help,

I noticed with this analog again and also with the bypass there is a dependecy with the freq,

higher freq has more gain then lower, so close to 20k it is high but 1k barely any gain, is this happening to you too? 

I trying to give a gain to a human voice range signal, like 1k and the results are bad so far. 

Hi Maikon,

Can you share an FFT of the frequency dependency you are seeing? I don't think I understand the issue well.

Best regards,
Jeff McPherson

I have some terrible images with the blue signal on bottom shows the signal frequency changing and the output in yellow on top you can see the signal amplitude going getting wider. can you vary the freq of your setup and check if there is any change in the signal amplitude ?

Hi Maikon,

I set up a path with the PGA, bypassed to Line Outs and I didn't get the frequency variation you're seeing. Did I misunderstand the set up?

w 30 01 80
w 30 07 80
w 30 18 F8
w 30 13 F8
w 30 16 F8
w 30 15 F8
w 30 13 C0
w 30 15 C0
w 30 56 98
w 30 5D 98
w 30 51 80
w 30 56 99

Best regards,
Jeff McPherson

tks again for your help, you understood the setup I can see your picture that changing the freq  does not change the gain, however you went from 72Hz to 631Hz, for me in this freq I barely have any signal. Also I still have my signal vanishing as the freq drops, even using your configuration registers. 

I noticed some of your registers are repeated, like w 30 13 F8 then w 30 13 C0 , and some others, is there any particular reason for that ?

Hi Jeff, can you try a feedback loop with the ADCs ?

Hi Maikon,

I'll be able to test your second set up sometime tomorrow.

In the mean time, the reason some of the registers repeat is because I made that script with the EVM GUI. So it's not fully optimized though I tried to keep it short. Also I did a full sweep and didn't see a frequency drop, I just had to zoom in on this particular section to demonstrate the effect. 

Have you double checked that the signal source is not being attenuated by some bandwidth before it makes it to the codec?

Best regards,
Jeff McPherson

ah okay, understood about the EVM GUI and repeated registers. 

yes , I have probbed the input pin of the MIC and initially not vanishing there, but I will check again, this effect has been happening even with the simple input to output configuration 

w 30 01 80
w 30 07 80
w 30 6C 02
w 30 6C 03

Okay,

I'll try again with the simpler bypass script and see if the effect appears. It seems to be high pass in nature. There's no filters in between the input pin and the source is there? As well as on the output?

Best,
Jeff McPherson

I do have a circuit in the input but I have been probing the MIC1LP  directly while  varying the freq and I have been seen same amplitude (that`s why I am not considering the problem being the circuit). 

Hi Maikon,

I see now what you're talking about. I'm not sure exactly what filtering may be going on in that path to be causing this internally to the device. However I did find that this doesn't happen if you use the PGA bypass path to the Line Outs.

w 30 01 80
w 30 07 80
w 30 13 40
w 30 15 40
w 30 18 F8
w 30 13 C0
w 30 16 F8
w 30 15 C0
w 30 51 80
w 30 56 98
w 30 56 99

Do you still need the ADC -> DAC loopback path checked? Do you have a script I can check with?

Best regards,
Jeff McPherson

Hi Jeff, that's my try:

reg, value
0, 0,
1, 0x80,
8, 1<<6 |1<<7,
86, 153,                           //LEFT_LOP/M Output Level Ctrl Reg with 9db of gain D7-D4
107, 1<<3,                       //SW-D1
101, 1,        //CODEC_CLKIN uses CLKDIV_OUT
15, 20,                 ///PGA D6-D0, 0 | 15, //20 gives 10db 31 give a gain of 15db
19, 1<<6 | 1<<2 ,    //D6-D3 1<<3 -1.5db 1<<6 -12db 40 -9db single ended mic and -12 db of gain LEFT_ADC ON
41, 1<<6,    //DAC_L3
7, 1<<3,    //Left-DAC data path plays left-channel input data.
37, 1<<7, //LEFT DAC ON
43, 0, //left DAC is not muted

using the ADC and DAC I am wondering if I can have the internal feedback loop shielded from this high pass filter effect. 

Hi Maikon,

Code looks okay to me. But if you're only concerned about avoiding the high pass effect to get analog bypass, I'd recommend the code I attached above. It uses the PGA, but skips the ADC and DAC. You'll save some power consumption that way. 

Best regards,
Jeff McPherson

Tks again, I tried but still had the same effect, but I am moving forward to use the I2S interface, just to confirm my configuration I am working with 48kHz of fs(ref), and MCLK of 12.288MHz via MCLK straight to CODEC_CLK (which is 256*fs(ref)), so I leave Q as the default 2.

Hi Maikon,

Ok. Are you intending to run this in slave mode or master mode?

Best regards,
Jeff McPherson

right now I am working with TLV in master mode , since the WCLK n BLK are output , but MCLK is being received by AIC3104 with 12.288 MHz and I am configuring to use the CLKVID_OUT side (not the PLL). 

Got it. In that case yes your settings seem appropriate. In case you have trouble with setting up Master Mode, you can use this calculator to help you set PLL and Divider Coefficients: https://www.ti.com/tool/download/SLAR163

Best regards,
Jeff McPherson

thank you, I just used it. So for 48kHz, I understood to have CODEC_CLK = 256*fsred gives the 12.288 MHz then Q = 2, using the CLK_DIV path. 

right ?

Hi Maikon,

Yes that's correct.

tks again Jeff, I am stil having my signal being attenuated for the low frequencies, and I am wondering if it is related to impedance.

Hi Maikon,

Is this still for the analog bypass path? It's possible the impedance of the source may be forming a filter. Is it a low impedance output? Do you have different source you can compare with?