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PCM1861: Interrupting I2S clock causes glitch on audio input line

Jim Teunis
Intellectual 290 points
Part Number: PCM1861


I'm running into an issue with the PCM1861 running as I2S slave. In a certain operation mode of our product, our main microcontroller (I2S master) will repeatedly briefly stop the I2S clock. When this happens, I observe that the input signal line briefly dips to ground (about 1 ms). If other devices are connected to the same input line, a popping noise is heard, which is undesirable. 

In the screenshots below, the upper trace is the audio input signal line (directly at the PCM1861 input), the bottom trace is the I2S LRCK coming from the microcontroller. It can be seen that the input starts to ramp down linearly and then ramps up logarithmically immediately after the I2S clock halts. The BCK clock is also halted at the same time.

All configuration pins are pulled to zero (directly connected to ground). Please see below for the schematic:

We are using 2 channels as single-ended audio source. They are connected exactly as in the datasheet with the additional anti aliasing filter, with the addition of one 100k resistor to ground, which I think might be redundant:

For reference, this is the input schematic from the PCM186x datasheet:

The dip is also observed if nothing is connected to the audio input. Therefore, the dip/glitch must be caused by the PCM1861.

What is causing the input to dip? And is there something we can do about it? We don't have full control over the I2S clock signal so we are not able to ensure it will also keep on running.

Thank you in advance for your help.

  • 0
    TI__Mastermind 23030 points

    I attempt an explaination . I am not sure its correct at the moment .

    When the clock is stopped the device gets a Clock error and goes into Standby Mode. To Save power in Standby Mode the Internal Biasing of the input pins is disconnected.

    Just before the removal of the clock, the 10u coupling capacitor is charged to a Voltage provided by the internal bias source of the IC. On removal of the clock the internal bias in the chip disconnects. The capacitor starts discharging and this is seen as a fall in the input pin DC Voltage.

    When the Clocks return the internal Bias Returns and re charges the Coupling capacitor back to the bias value (Maybe V/2).

     What exactly do you mean when you say other inputs are disturbed? Are there other  circuits connected to the input side of C72?

    ------------------------------------------------------------------------------

    You can try some things here to keep the input from disturbing:

    1. A pullup to 3.3v /2 can be attempted on the input pin. This will try to  keep the voltage stable on the input pin even if clock go away.

    2. The 10u input to this ADC can be fed through the output of  a Unity gain op amp buffer.Other circuits can be connected to the input of the Buffer. This would ensure that they do not see any loading due to switching off the clock. 

  • +1 in reply to Sanjay Dixit
    Intellectual 290 points

    Thanks for your reply.

    Indeed there can be another circuit connected to the input side of C72. The idea is to have to a passive pass-through, that also works when our device is powered off.

    After reading your reply, I also suspect it will be something along those lines. The 100k resistor that I called "maybe redundant" in my first post was meant to always pull the signal to the neutral level, however at that time we were working with a differential signal. Perhaps running the 100k resistor to VREF instead of GND will do the trick. I will try this and report back.

  • 0 in reply to Jim Teunis
    TI__Mastermind 23030 points

    Yes please do try that.

    Also a Pullup  of 22k from input pin to a dc Supply of 1.65v can be something also tried. It would be interesting to see what this does when the clock is stopped .

  • 0 in reply to Jim Teunis
    Intellectual 290 points

    Thanks for your reply.

    Indeed there can be another circuit connected to the input side of C72. The idea is to have to a passive pass-through, that also works when our device is powered off.

    After reading your reply, I also suspect it will be something along those lines. The 100k resistor that I called "maybe redundant" in my first post was meant to always pull the signal to the neutral level, however at that time we were working with a differential signal. Perhaps running the 100k resistor to VREF instead of GND will do the trick. I will try this and report back.

    EDIT:

    I have removed the 100k resistor to ground on one PCB and that has fixed the issue. The interruptions in I2S clock are about 1 second long, and this is short enough to keep the voltage on the ADC input pin almost the same so the popping is gone.

    Thanks for your reply!