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TLV320AIC3100: Beep generator output a frequence of 320kHz regarding the configuration

Ruben Anidjar
Prodigy 10 points
Part Number: TLV320AIC3100


Hi, 

I'm trying to use the beep generartor on the TLV320AIC3100.
The chip output a square wave of 320Khz since I set register 71 D7 to 1. the signal is continous as the beep length register are not read.
I use a 12Mhz MCLk with the associate PLL as input clock.
I read back the register and all seem correct. I found out that  "DAC PGA applied gain = programmed gain " in register 38 D4 and D1 stay at 0 indefinitly.

my configuration :

/*page 0*/
I2CSend(0,0);
I2CSend(1, 0x01);
usleep(1000);
/*page 3*/
I2CSend(0,3);
I2CSend(16,0x0C);//1MHz on internal RC
/*page 0*/
I2CSend(0,0);
I2CSend(4, 0x03);
I2CSend(5, 0x91);
I2CSend(6, 0x07);
I2CSend(7, 0x06);
I2CSend(8, 0x90);
I2CSend(11, 0x82);
I2CSend(12, 0x87);
I2CSend(13, 0x00);
I2CSend(14, 0x80);
I2CSend(18, 0x87);
I2CSend(19, 0x82);
I2CSend(20, 0x80);
I2CSend(25, 0x03);
I2CSend(27, 0x00);
I2CSend(60, 0x19);
I2CSend(63, 0xFC);
I2CSend(64, 0x00);
I2CSend(65, 0x30);
I2CSend(66, 0x30);
I2CSend(72, 0xC0);
I2CSend(73, 0x17);
I2CSend(74, 0x70);
I2CSend(75, 0x00);
I2CSend(76, 0x21);
I2CSend(77, 0x21);
I2CSend(78, 0x7B);
I2CSend(79, 0xA3);
/*go to Page 1*/
I2CSend(0, 0x01);
/*Page 1*/
I2CSend(32, 0x86);
I2CSend(35, 0x40);
I2CSend(38, 0x80);
I2CSend(42, 0x1C);
/*Page 0*/
I2CSend(0, 0x00);
//I2CSend(71, 0x80);

  • 0
    TI__Mastermind 29755 points

    Hi,

    You can refer to the following apps. note for beep generation example.

    https://www.ti.com/lit/an/slaa446/slaa446.pdf?

    Regards.

  • 0 in reply to pdjuandi
    Prodigy 10 points

    Hi, ,

    I try the example in the application note with the 44.1Khz sampling frequency and I still got that 320kHz signal on the output. I change the PLL value for corresponding sample frequency as well.

    Do you have any other suggestion ?

  • 0 in reply to Ruben Anidjar
    TI__Mastermind 29755 points

    The example calculation is based on 48KHz Fs, can you use the same sine/cosine coefficient in the example since your register above is also based on 48KHz?

    Also this is target/slave mode, so right now ensure no data is coming in from the host maybe remove the DIN input.

    Check your WCLK and BCLK also.

  • 0 in reply to pdjuandi
    Prodigy 10 points

    As specify in Appendix A of the application note the sampling frequency is 44.1KHz

    also I redo the calculation on MATLAB for Fs = 44.1Khz and I obtain the same value as those wrtitten in the AP.



    if I change the Fs for 48Khz I obtain the value I input in my previous message



    As for BCLK and WLCK no I2S  transmitter is running during the test. Are those signal mandatory for using the beep generator ?


    I also found contradiction bettween the AP and the DataSheet. In section 7.3.10.7 of the datasheet it say that we need to power down Ndac and mute DAC before playing the beep but none of this is mention in the AP.

    Also the data sheet says that we should provide a 1MHz clock for "various internal timing intervals, debounce logic and interrupts" Why the AP skiping this part ?

  • 0 in reply to Ruben Anidjar
    TI__Mastermind 29755 points

    It's OK if you have checked that, because I see it's using 48Khz here in the beep length.

    Device is in slave/target mode so it needs the WCLK and BCLK.

    If you have the EVM, you can try the beep function which allows setting the frequency and duration.

    I'm using an EVM from similar device and I can hear the beep tone at the output. This command below shows only the beep settings, you still need to configure the DAC path.

    The apps. note gives example of configuring the beep only, it does not configure the signal chain.

    So maybe what you should do first is to confirm your DAC path is working, then add the beep. 

    In the datasheet it gives an example for doing that.

    Regards.

  • 0 in reply to pdjuandi
    Prodigy 10 points

    Hi ,

    So I finally got a beep from the device. 
    To do so I re-routed BCLK and WCLK to be generate from the device (master mode). I was missing a the setting of the register 30 page that enable BCLK divider and let the clock run.