• State
  • Locked Locked
  • Replies 4 replies
  • Subscribers 32 subscribers
  • Views 409 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TAS5720A-Q1EVM: I2S clocks and its frequencies

Mohit Manvar
Prodigy 90 points
Part Number: TAS5720A-Q1EVM

Hello,

I have some questions below:

1) why MCLK is used and does it require for I2S transmission or I2C communication?

2) Why MCLK frequency need in sync with I2S peripheral clock frequencies?

     please share some reference material for our better understanding.

3) How much deviation allowed in clock frequencies?

  we have following frequencies need and we achieved.

clock required achieved
MCLK 4.096MHz 4.005MHz
SCLK 1.024MHz 1.007Hz
LRCK 32KHz 31.11KHz
  • 0
    TI__Mastermind 49750 points

    Hi Mohit

       The MCLK is the main clock for this device, all the digital circuit rely on this clock to work, including I2S circuit. Internally the circuit will follow the MCLK to read the I2S signal, not following the frequency requirement may results incorrect signal.

       The clock frequency usually could accept ±10% variation. 

  • 0 in reply to Shadow He
    Prodigy 90 points

    Hello

    thanks for reply.

    I have another query.

    when I'm reading registers via I2C, error status register is giving Clock error (0x8) in response. so what can be cause of that even though all my clocks are having same frequencies as described above and all are in multiple of Fs.

    As per datasheet, it is non-latching error so how can I get back to valid state?

    BR, Mohit

  • 0
    Prodigy 90 points
    Mohit Manvar said:
    2) Why MCLK frequency need in sync with I2S peripheral clock frequencies?

    can you suggest solution for this? can I get detailed reference for frequencies and its characteristics?.

  • 0 in reply to Mohit Manvar
    TI__Genius 15080 points

    Hello Mohit,

    This device uses 4-wire I2S so MCLK is a requirement. What are you using to drive the current I2S source? is there a reason your clocks are deviated from the expected value that much. Also if you change LRCLK to a more standard value like 44.1 or 48 is the same behavior observed?

    Below is the mechanism for the Clock Error Detection.

    1. Non-Supported MCLK to LRCK and/or SCLK to LRCK Ratio (1fs to detect error and 40fs to clear error) 

    2. Non-Supported MCLK or LRCK rate (~1us to detect error and ~1ms to clear error)

    3. MCLK, SCLK or LRCK has stopped (~1us to detect error and ~1ms to clear error)

    best regards,
    Luis