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TLV320DAC3203EVM-K: Configuring the clocks for 48kHz

gustavo zarba
Expert 1110 points
Part Number: TLV320DAC3203EVM-K

Hi dear people!

Sorry, I need more explanations or help.

The example presets on the GUI are for 44.1kHz use.
I would like to work with 48kHz and with a rather low MCLK frequency of 2.048MHz. (This is the frequency coming from the MCU to the MCLK pin of the DAC on my board)
By the way, the GUI actually does not have to "work", but only serve as a sort of script generator.

Table 2-23 (page 66 on SLAU434A) shows the following register values for this:
// PLL Configuration for fS = 48kHz
// MCLK (MHz) PLLP PLLR PLLJ PLLD MADC NADC AOSR MDAC NDAC DOSR
// 2.048                1        3       14       0        2          7       128      7          2        128

I was hoping to use the GUI to configure all this safely, but I cannot achieve the desired sample rate fS of 48kHz
Using the values of the table, I get DAC_FS = 48.7619kHz

Writing directly to the register, yes, I could try, but I would feel more comfortable by relying on the GUI.

Could you please guide me through this?

Best regards,

Gustavo

  • +1
    TI__Guru* 98235 points

    Hi Gustavo,

    There may be some minor disconnect here. I verified these values at the GUI on my end and the resulting DAC_FS matches with expected 48kHz. Could you please share captures similar to these?

    Best regards,
    -Ivan Salazar
    Applications Engineer

  • 0 in reply to Ivan Salazar
    Expert 1110 points

    Hi Ivan,

    Solved!

    I don't know it it was relevant, but I connected the EVM this time to the Host.
    The difference to your setting was, that I had (in the first screenshot from you) the 2.048MHz in both places (Codec Input Clock AND PLL Input Clock) and by the selector underneath I had MCLK instead of PLL_CLK
    By the Dividers I had the 'Power' selectors on both sides.

    Now, by your settings, I get the 48kHz too.

    Also I have some question to the shut-down procedure, but I will initiate a new poe for this.

    I think, I have to re-re-re-read the specs again. The setting of the PLL is not really clear for me.

    Many thanks and I wish you a fine Weekend!

    Gustavo