TLV320AIC3204: I2S 24bit "DAC" is inoperative.

Lee Dongji

Part Number: TLV320AIC3204

② #B to #A is normal.

① The voice received by Din(I2S 24bit) passes through the DAC and is not heard from the HPL. Is there anything I set wrong in the register below?

The register below is the register of #A.
The register of #B differs only by "0x1BC0".
(length of Audio Interface LJF - 16bit)

I couldn't hear the sound from HPL of #A, so I didn't check the ADC operation of #B.

u16 codec_initial_CH1_2[CODEC_SIZE] =
{
// MCLK = 11.2896Mhz(WCLK * 256) / BCLK = 2.8224Mhz(WCLK * 64) / WCLK = 44.1khz
// MCLK = 12.288 Mhz(WCLK * 256)) / BCLK = 3.072 Mhz(WCLK * 64) / WCLK = 48khz
// MCLK = 12.288 Mhz(WCLK * 128) / BCLK = 6.144 Mhz(WCLK * 64) / WCLK = 96khz
// PCM 24 Fix
////////////////Page 0////////////////// Example Page 87
0x0000, // Page 0
// 0x0101, // Reset
// 0x02~0x03, 0x06~0x08 PLL 설정.
0x0400, // MCLK pin is CODEC_CLKIN
///////////////DAC Set////////////////////
0x0B81, // NDAC = 1
0x0C82, // MDAC = 2
0x0D00, // OSR of DAC - 1
0x0E80, // OSR of DAC - 2 OSR = 128
0x1B20, // length of Audio Interface I2S - 24bit
0x3C01, // DAC - PRB_P1

///////////////ADC Set////////////////////
0x1281, // NADC // NDAC 값 사용.
0x1382, // MADC // MDAC 값 사용.
0x1480, // OSR of ADC - AOSR = 128 (Use with PRB_R1 to PRB_R6, ADC Filter Type A)
0x3D01, // ADC - PRB_R1

// 0x1900, // 사용 X
// 0x1A00, // 사용 X

// 0x1C00, // Data offset setting
// 0x1D00, // Loopback
// 0x2000, // Audio Interface 5 이해가 안되는 reg
// 0x2100, // Audio Interface 6 이해가 안되는 reg
// 0x24 ~ 0x2F // Read 전용

////////////////Page 1//////////////////
0x0001, // Page 1
0x0108, // Avdd On
0x0200, // Analog Blocks Enabled

///////////////DAC Set////////////////////
0x0300, // HPL uses Class-AB driver / PTM_P3
0x0400, // HPR uses Class-AB driver / PTM_P3
0x0930, // HPL, HPR Power On / LOL, LOR Off
0x0C08, // HPL - DAC Left routed
0x0D08, // HPR - DAC Right routed

0x1000, // HPL - Gain 0dB ★ Analog Gain // Mute - 0x1040
0x1100, // HPR - Gain 0dB ★ Analog Gain // Mute - 0x1140
0x1425, // Headphone Driver Startup 잘 모르겠음..예제따라함.
0x1675, // IN1L to HPL Volume Control -Mute
0x1775, // IN1R to HPR Volume Control -Mute
0x1828, // Mixer Amplifier Left Volume - Mute
0x1928, // Mixer Amplifier Right Volume - Mute

///////////////ADC Set////////////////////
0x0A00, // Full Chip Common Mode is 0.9V
0x3D00, // PTM_R4
0x4732, // Analog inputs power up time is 3.1 ms
0x7B01, // Reference will power up in 40ms when analog blocks are powered up
0x34C0, // IN1L Left MICPGA - 40k resistance
0x36C0, // CM is routed to Left MICPGA via CM1L with 40k resistance
0x37C0, // IN1R Right MICPGA - 40k resistance
0x39C0, // CM is routed to Right MICPGA via CM1R with 40k resistance
0x3B80, // Left MICPGA ★ Analog Gain
0x3C80, // Right MICPGA ★ Analog Gain

// 0x3E ~ 0x46 // Read 전용
////////////////Page 0//////////////////
0x0000, // Page 0
0x3FD6, // Left, Right DAC Power On
0x4000, // Left, Right DAC Not Muted
0x4100, // DAC Left Digital Volume 0dB ★
0x4200, // DAC Right Digital Volume 0dB ★

0x51C0, // Left, Right ADC Power On
0x5200, // Left, Right ADC Not Muted
0x5300, // Left ADC Digital Channel Volume 0dB ★
0x5400, // Right ADC Digital Channel Volume 0dB ★
};

over 1 year ago

0 pdjuandi over 1 year ago

TI__Mastermind 29755 points

Hi,

I see some of the settings are commented out or not shown here like page 0 register 0x1B which sets the audio format and bit depth.

Can you tell me what's the MCLK, WCLK you are trying to run with and show me the active registers for example remove those comment if you are using them?

From just the above as it is, it will not work. Are these in slave mode?

Regards.

0 Lee Dongji over 1 year ago in reply to pdjuandi

Prodigy 40 points

Hello.

#A standpoint

IN1_L(Analog) -> ADC (I2S, 24bit) -> Dout (normal)
Din -> DAC (I2S, 24bit) -> HPL (failed)

I don't know if I understood your request correctly.
I'm writing again as I understand.

For #A, I2S, 24 bits is fixed (44.1kzh, 48khz, 96khz, 16bit)
For #B, LJF, 16 bits is fixed (32khz, 16bit)

For #A : MCLK, BCLK, and WCLK are used in three cases.

case 1
MCLK = 11.2896Mhz
BCLK = 2.8224Mhz
WCLK = 44.1khz

case 2
MCLK = 12.288Mhz
BCLK = 3.072Mhz
WCLK = 48khz

case 3
MCLK = 12.288Mhz
BCLK = 6.144Mhz
WCLK = 96khz

I deleted all the comments and left only the actual registers.

Operated as SPI, TLV320AIC3204 is in Slave Mode.

In the case of I2S, the external device is Master.
MCLK, BCLK, and WCLK are also supplied from external devices.

TLV320AIC3204 is a slave.

#A Oscilloscope
1CH (Yellow): WCLK
2CH (Sky Blue): Din
3CH (Purple): Dout

u16 codec_initial_CH1_2[CODEC_SIZE] =
{
// MCLK = 12.288 Mhz(WCLK * 256)) / BCLK = 3.072 Mhz(WCLK * 64) / WCLK = 48khz
// PCM 24 Fix
////////////////Page 0////////////////// Example Page 87
0x0000,
0x0400,

///////////////DAC Set////////////////////
0x0B81,
0x0C82,
0x0D00,
0x0E80,
0x1B20,
0x3C01,

///////////////ADC Set////////////////////
0x1281,
0x1382,
0x1480,
0x3D01,

////////////////Page 1//////////////////
0x0001,
0x0108,
0x0200,

///////////////DAC Set////////////////////
0x0300,
0x0400,
0x0930,
0x0C08,
0x0D08,
0x1000,
0x1100,
0x1425,
0x1675,
0x1775,
0x1828,
0x1928,

///////////////ADC Set////////////////////
0x0A00,
0x3D00,
0x4732,
0x7B01,
0x34C0,
0x36C0,
0x37C0,
0x39C0,
0x3B80,
0x3C80,

////////////////Page 0//////////////////
0x0000,
0x3FD6,
0x4000,
0x4100,
0x4200,

0x51C0,
0x5200,
0x5300,
0x5400,
};

Regards.

0 pdjuandi over 1 year ago in reply to Lee Dongji

TI__Mastermind 29755 points

Can you check if AVDD is present and what's the voltage? How do you provide DIN and what's the HP load?

The register looks ok see my comment in the attached file.

Fullscreen 5635.register.txt Download

u16 codec_initial_CH1_2[CODEC_SIZE] =
{
// MCLK = 12.288 Mhz(WCLK * 256)) / BCLK = 3.072 Mhz(WCLK * 64) / WCLK = 48khz
// PCM 24 Fix
////////////////Page 0////////////////// Example Page 87
0x0000,
0x0400,	// PLL_CLKIN=MCLK, CODEC_CLKIN=MCLK

///////////////DAC Set////////////////////
0x0B81,	// NDAC=1 powered up
0x0C82,	// MDAC=2 powered up
0x0D00,	// MSB DOSR=0
0x0E80,	// DOSR=128
0x1B20,	// I2S, 24 bits, slave mode
0x3C01,	// PRB_P1

///////////////ADC Set////////////////////
0x1281,	// NADC=1 powered up
0x1382,	// MADC=2 powered up
0x1480,	// AOSR=128
0x3D01,	// PRB_R1

////////////////Page 1//////////////////
0x0001,
0x0108,	// Disabled AVDD to DVDD -> AVDD is powered and provided externally
0x0200,	// DVDD=1.72V, Analog block enabled, AVDD LDO powered down

///////////////DAC Set////////////////////
0x0300,	// Left DAC to HPL with class-AB
0x0400,	// Right DAC to HPL with class-AB
0x0930,	// HPL and HPR powered by AVDD
0x0C08,	// Left DAC + term to HPL
0x0D08,	// Right DAC + term to HPR
0x1000,	// HPL not muted with 0dB gain
0x1100,	// HPR not muted with 0dB gain
0x1425,	// HP driver ramp up 5 Tc
0x1675,	// IN1L to HPL volume muted
0x1775,	// IN1R to HPR volume muted
0x1828,	// MAL volume muted
0x1928,	// MAR volume muted

///////////////ADC Set////////////////////
0x0A00,	// CM=0.9V for HPL and HPR powered with AVDD
0x3D00,	// Powertune PTM_R4
0x4732,	// Analog input powered up in 6.4ms
0x7B01,	// Reference power up in 40ms
0x34C0,	// IN1L to Left PGA with 40K
0x36C0,	// CM to Left PGA with 40K
0x37C0,	// IN1R to Right PGA with 40K
0x39C0,	// CM to Right PGA with 40K
0x3B80,	// Left PGA Gain = 0dB
0x3C80,	// Right PGA Gain = 0dB

////////////////Page 0//////////////////
0x0000,
0x3FD6,	// Left and Right DAC powered up 
0x4000,	// Left and Right DAC not muted
0x4100,	// Left Digital volume = 0dB
0x4200,	// Right Digital volume = 0dB

0x51C0,	// Left and Right ADC powered up
0x5200,	// Left and Right ADC not muted with gain = 0dB
0x5300,	// Left ADC volume = 0dB
0x5400,	// Right ADC volume = 0dB

If AVDD is correct and still there's no output on HP, can you try LINEOUT or using AVDD_LDO?

Are you seeing this on several devices/setup?

Regards.

Audio

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TLV320AIC3204: I2S 24bit "DAC" is inoperative.