Other Parts Discussed in Thread: DRV5825P
Hi there,
The goal of our project is to build an amplifier for a parametric speaker (ultrasonic transducer array).
Wherefore, we need to amplitude-modulate the carrier frequency of 40kHz with the audio signal (base-band).
The required bandwidth is ±5 kHz (35 kHz ... 45 kHz), which theoretically fits into the Nyquist-band of fs/2 (at 96 kHz sample rate -> BW = 48kHz).
The DRV5825P seems so be ideal for this task, as it is specially designed for capacitive piezo-electric transducers and has a loop-bandwidth (output bandwidth?) of up to 175 kHz @ Fsw 768 kHz (switching frequency).
So in theory it should be able to reproduce a output frequency of 40 kHz.
However, while testing the evaluation board, we've never were able to produce higher frequencies above ~25 kHz.
We confirmed that the input sample rate is set to 96 kHz (LRCLK measured) and the chip correctly detects it (FS_MON Register 37h -> FS = 4'b1011).
In the Pure Path Console 3 Tool, the internal sampling rate can only be set to 48 kHz (which of course is too low).
Therefore we adjusted the registers directly by setting the DSP_CTRL Register 46h -> USER_DEFINED_PROCESSING_RATE = 2'b00 (same as input, no sample rate conversation).
This didn't really help to solve the issues.
My hypothesis is that even when the pre- and post EQs are disabled, there are still some filters (interpolation?) build into the internal signal chain that have a low-pass characteristic.
My question is therefore: Is it possible to use this chipset for our application? If yes, how do i need to configure it to get the full bandwidth of up to 48 kHz (@ 96 kHz sample rate)?
I hope the information I've provided is sufficient to answer my questions.
Thanks in advance for the support!
Florian
