PCM1794A: Clock timing when using mono mode

Hello Tom,

Please refer to figure 22 part3 where it shows how I2S signals and timings are supposed to be. This is a stereo part so the right channel data is at the rising edge of the LRCLK and left channel data is presented at the falling edge of the LRCLK. You can apply the same data at both channels or just to one channel as long as you are in following the diagram in figure 22 for I2S format.

Regards,

Arash

I understand how I2S works and have read the data sheet. The information I'm missing is when the data are presented to the DAC itself, internal to the chip, in particular in mono mode.

Maybe I should ask my question differently:

With the PCM179x in mono mode one DAC handles the left channel and the other handles the right channel. If I feed the two DACS the same BCK, SCK, LRCLK, and DATA will the two DACs be in sync? I.e., if a sine wave stimulus is presented digitally to the DACs will the left and right channels be in the exact same phase or will there be a 1/(2*fs) delay between them?

I'm asking because I've seen some circuits where the designer has gone through quite a bit of trouble to delay one channel relative to the other using a shift register. I'm assuming this is unnecessary, but thought I'd ask before I spend money on DAC ICs and PCBs.

Tom