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PCM1820-Q1: I2S output format in master mode

Jass Jin
Intellectual 2505 points
Part Number: PCM1820-Q1


Hi expert,

I didn't see clear detail about I2S format config in datasheet, only MD0 for master clock, does BCLK always 64 times the FSYNC frequency? Is 44.1kHz or 48kHz sample frequency realized by input MCLK(divide 256/512)?

Does below picture mean TDM format can support 2-ch or 4-ch output, in different FMT0 config?

  • 0
    TI__Mastermind 27700 points

    Hi Jin,

    1.Master mode operation supported using a system clock of 256 × fS or 512 × fS and only supports fS rates of 44.1 kHz and 48 kHz.

    2. PCM1820-Q1 is a 2CH ADC. But to help visualize L/R data slots of the audio signal, illustrators will use a channel designation. For instance in the case of 8-3, CH1 is CH1 ADC left, "CH2" is CH1 ADC right, "CH3" is CH2 left...etc.

    Figure 8-3 is essentially a format of TDM where it supports 4 slots of data, 8-4 supports 2 slots.

    Regards,