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PCM3070: random shut-off

Part Number: PCM3070

I'm having some issues with the PCM3070 audio CODEC. The I2C commands work and sound can be heard fine after being configured. However, about every 60s the outputs of the PCM3070 will shut off for ~1s and then turn on again. This process repeats infinitely. The noise floor is also high and changes according to the DAC gain of the PCM3070. When the device shuts off randomly every ~60s, the noise floor can still be heard from the PCM3070. I've confirmed that it is not an issue with the output stage amplifier (TDA7375AV) or the source (BTM875-E, CSR8675 Bluetooth module via I2S). The CSR8675 will go into a mute state when sound stops playing from the wireless source device and the loud noise floor stops when this happens (the PCM3070 PLL gets its clock from BCLK from the I2S of the CSR8675, 18.432MHz clock). When I disconnect the PCM3070 from the output stage amplifier, the noise floor also disappears. The power supply I am using for this application is a switching laptop power supply rated at 16.5V, 4.5A. I believe all filtering caps that are needed are included in the schematic. Please let me know otherwise. Attached is the .cfg from PurePath and the schematics. Thanks.

EDIT:

The high noise floor has been suppressed. I used 2x 470Ω between R4, R5 to AGND. I also decreased the PCM3070 outputs to 0dB each and then increased the digital gain from the CSR8675. All this made the noise floor impossible to hear from normal listening distances. The shut-off every ~60s still occurs though.

6840.base_main_Rate48.cfg

  • Hi,

    It looks like the clocks stop; can you monitor the ASI bus?

    I think when the source sound stops, the host stops providing the clocks to the codec.

    Regards.

  • monitor the ASI bus

    Where is the ASI bus? Do you mean the BCLK I2S pin?

    Goose

  • Yes, monitor WCLK, BCLK.

  • Here are the results:

    BCLK:

    WCLK:

    Neither of these clocks stop when the shut-off occurs during playback. I also looked at DOUT of the CSR8675 and it doesn't stop at all either.

  • Perhaps my PLL config is incorrect? I just used the defaults from PurePath. I am using both miniDSP A and D, which requires the ADC to be powered on. Is this configuration correct? (starting at line 10247 from 'base_main_Rate48.cfg' attached above):

    #            # reg[  0][  5] = 0x91    ; P=1, R=1, J=8
    w 30 05 91
    #            # reg[  0][  6] = 0x08    ; P=1, R=1, J=8
    > 08
    #            # reg[  0][  7] = 0x00    ; D=0000 (MSB)
    > 00
    #            # reg[  0][  8] = 0x00    ; D=0000 (LSB)
    > 00
    #            # reg[  0][  4] = 0x07    ; PLL_clkin = BCLK, codec_clkin = PLL_CLK, PLL on
    w 30 04 07
    #            # reg[  0][ 12] = 0x88    ; MDAC = 8, divider powered on
    w 30 0c 88
    #            # reg[  0][ 13] = 0x00    ; DOSR = 128 (MSB)
    > 00
    #            # reg[  0][ 14] = 0x80    ; DOSR = 128 (LSB)
    > 80
    #            # reg[  0][ 11] = 0x82    ; NDAC = 2, divider powered on
    w 30 0b 82
    #            # reg[  0][ 81] = 0xc0    ; Power up LADC/RADC
    w 30 51 c0
    #            # reg[  0][ 82] = 0x00    ; Unmute LADC/RADC
    > 00

  • So the clocks do not stop and resume when this happens?

    Your PLL setting is not correct for BCLK=18.432MHz and Fs=48KHz. This should be the dividers as shown in this PLL calculator.

    You can download this calculator from the product folder below.

    TLV320AIC3254-Q1 data sheet, product information and support | TI.com

    Regards.

  • I've tried absolutely everything. I fixed the PLL, swapped out the chip entirely with a new one, and even swapped out the CSR8675 just for a sanity check. I finally discovered it was one of the filters in the PurePath Studio that's bugged. Once I removed all processing blocks and just passthrough the stream to the DAC, everything worked perfectly. I will try to make a new PurePath DSP config. Thank you for your help.