TLV320AIC3204: Not able to play/capture audio on headphone

Jalpan Parekh

Prodigy 10 points

Part Number: TLV320AIC3204

Hi,

Host Processor: QCS8550 LE

Audio codec: TLV320AIC3204

MI2S interface: MI2S1

Pins configured: SD0 --> DIN, SD1 --> DOUT

To play audio following mixer controls configured:

qtitinymix "HPL Output Mixer L_DAC Switch" 1
qtitinymix "HPR Output Mixer R_DAC Switch" 1
qtitinymix "HP DAC Playback Switch" 1
qtitinymix "HP Driver Gain Volume" 35
qtitinymix "PCM Playback Volume" 50

To capture audio following mixer controls configured:

qtitinymix "Mic PGA Switch" 1
qtitinymix "IN1_L to Left Mixer Positive Resistor" 1
qtitinymix "ADCFGA Left Mute Switch" 0
qtitinymix "AGC Left Switch" 1
qtitinymix "ADC Level Volume" 64
qtitinymix "PGA Level Volume" 95
qtitinymix "AGC Max PGA" 60
qtitinymix "AGC Noise Threshold" 31

# agmplay /data/mask-100-550.wav -D 100 -d 100 -i MI2S-LPAIF-RX-SECONDARY

When I am playing audio I can see the data on DIN pin but not able to hear the audio on headphone.

Please guide us for play/capture audio. Also confirm the mixer controls we have used.

over 1 year ago

0 pdjuandi over 1 year ago

TI__Mastermind 29755 points

Hi,

We're not Linux expert, have you contacted the host processor for support?

Regards.

0 Jalpan Parekh over 1 year ago

Prodigy 10 points

Hi,

I wanted to confirm the mixer commands for the play and capture. Can you please confirm the mentioned mixer commands are correct and enough to play/capture audio.

Thanks

0 Shenghao Ding over 1 year ago in reply to Jalpan Parekh

TI__Genius 11640 points

The mixer commands seemed OK, Kindly dump all the mixer control to me, and measure the bck and WS clk with scope to check whether the clk is OK

0 Jalpan Parekh over 1 year ago in reply to Shenghao Ding

Prodigy 10 points

Hi,

I have probed the clock and data lines.

BCLK: ~1.5 MHz (For 48KHz, stereo, 16-bit audio)

WCLK: ~48 KHz

MCLK: 11.2896 MHz

DIN: We can see the data while playing audio.

looks like it is as expected.

Please suggest what we can check now?

0 Shenghao Ding over 1 year ago in reply to Jalpan Parekh

TI__Genius 11640 points

Kindly use following commands.

amixer scontents

amixer controls

0 Jalpan Parekh over 1 year ago in reply to Shenghao Ding

Prodigy 10 points

amixer gives error.

/ # amixer scontents
Failed to create secure directory (/home/root/.config/pulse): No such file or directory
ALSA lib ../../alsa-plugins-1.2.6/pulse/pulse.c:242:(pulse_connect) PulseAudio: Unable to connect: Connection refused

amixer: Mixer attach default error: Connection refused

But we can get the mixer controls using qtitinymix commands:

292 INT 2 PCM Playback Volume 130 130
293 ENUM 1 DAC Left Playback PowerTune Switch P3
294 ENUM 1 DAC Right Playback PowerTune Switch P3
295 INT 2 HP Driver Gain Volume 35 35
296 INT 2 LO Driver Gain Volume 6 6
297 BOOL 2 HP DAC Playback Switch On On
298 BOOL 2 LO DAC Playback Switch Off Off
299 ENUM 1 LO Playback Common Mode Switch Full Chip
300 BOOL 2 Mic PGA Switch On On
301 BOOL 1 ADCFGA Left Mute Switch Off
302 BOOL 1 ADCFGA Right Mute Switch On
303 INT 2 ADC Level Volume 64 64
304 INT 2 PGA Level Volume 95 95
305 INT 1 Auto-mute Switch 0
306 BOOL 1 AGC Left Switch On
307 BOOL 1 AGC Right Switch Off
308 INT 2 AGC Target Level 0 0
309 INT 2 AGC Gain Hysteresis 0 0
310 INT 2 AGC Hysteresis 0 0
311 INT 2 AGC Noise Threshold 31 31
312 INT 2 AGC Max PGA 60 60
313 INT 2 AGC Attack Time 0 0
314 INT 2 AGC Decay Time 0 0
315 INT 2 AGC Noise Debounce 0 0
316 INT 2 AGC Signal Debounce 0 0

393 BOOL 1 HPL Output Mixer L_DAC Switch On
394 BOOL 1 HPL Output Mixer IN1_L Switch Off
395 BOOL 1 LOL Output Mixer L_DAC Switch Off
396 BOOL 1 HPR Output Mixer R_DAC Switch On
397 BOOL 1 HPR Output Mixer IN1_R Switch Off
398 BOOL 1 LOR Output Mixer R_DAC Switch Off
399 ENUM 1 IN1_R to Right Mixer Positive Resistor Off
400 ENUM 1 IN2_R to Right Mixer Positive Resistor Off
401 ENUM 1 IN3_R to Right Mixer Positive Resistor Off
402 ENUM 1 IN2_L to Right Mixer Positive Resistor Off
403 ENUM 1 CM_R to Right Mixer Negative Resistor 10 kOhm
404 ENUM 1 IN1_L to Right Mixer Negative Resistor Off
405 ENUM 1 IN3_L to Right Mixer Negative Resistor Off
406 ENUM 1 IN1_L to Left Mixer Positive Resistor 10 kOhm
407 ENUM 1 IN2_L to Left Mixer Positive Resistor Off
408 ENUM 1 IN3_L to Left Mixer Positive Resistor Off
409 ENUM 1 IN1_R to Left Mixer Positive Resistor Off
410 ENUM 1 CM_L to Left Mixer Negative Resistor 10 kOhm
411 ENUM 1 IN2_R to Left Mixer Negative Resistor Off
412 ENUM 1 IN3_R to Left Mixer Negative Resistor Off
413 BOOL 1 SWR DAC_Port Switch Off

0 Shenghao Ding over 1 year ago in reply to Jalpan Parekh

TI__Genius 11640 points

Also dump the register during playback with i2cdump, thanks.

0 Shenghao Ding over 1 year ago in reply to Jalpan Parekh

TI__Genius 11640 points

One more thing, have you set the codec as slave or master?

0 Jalpan Parekh over 1 year ago in reply to Shenghao Ding

Prodigy 10 points

Yes, it is configured.

0 Jalpan Parekh over 1 year ago in reply to Shenghao Ding

Prodigy 10 points

Can you explain more about register during playback with i2cdump. Because resource is already busy, so i2cdump will not work.

0 Jalpan Parekh over 1 year ago in reply to Jalpan Parekh

Prodigy 10 points

Ok I Got it.

/data # ./i2cdump -fy 3 0x18
No size specified (using byte-data access)
WARNING! This program can confuse your I2C bus, cause data loss and worse!
I will probe file /dev/i2c-3, address 0x18, mode byte
Continue? [Y/n] Y
0 1 2 3 4 5 6 7 8 9 a b c d e f 0123456789abcdef
00: 00 00 60 00 03 91 08 1b a2 00 00 88 82 00 80 02 ..`.?????..??.??
10: 00 08 88 82 80 01 00 04 00 00 01 00 00 01 88 00 .?????.?..?..??.
20: 00 00 00 00 44 aa 00 00 00 00 00 00 c0 00 00 00 ....D?......?...
30: 00 00 00 00 0a 12 03 02 04 00 00 00 01 01 00 d8 ....?????...??.?
40: 00 03 03 00 6f 38 00 00 00 00 00 ee 10 d8 7e e3 .??.o8.....???~?
50: 00 00 08 28 28 00 80 3e 3c 00 00 00 00 00 00 3e ..?((.?><......>
60: 3c 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 <...............
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................

0 Shenghao Ding over 1 year ago in reply to Jalpan Parekh

TI__Genius 11640 points

TLV320AIC3204 Application Reference Guide

B0P0x2C tells me the HPL/R is over-current.

Kindly dump page 1 register too, commands as follow, I want to get P1R3, P1R4

i2cset -fy 3 0x18 0 01

i2cdump -fy 3 0x18

0 Jalpan Parekh over 1 year ago in reply to Shenghao Ding

Prodigy 10 points

/data # ./i2cset -fy 3 0x18 0 01
WARNING! This program can confuse your I2C bus, cause data loss and worse!
I will write to device file /dev/i2c-3, chip address 0x18,
data address 0x00, data 0x01, mode byte.
Continue? [Y/n] Y
/data #
/data #
/data # i2cdump -fy 3 0x18
/bin/sh: i2cdump: not found
/data # ./i2cdump -fy 3 0x18
No size specified (using byte-data access)
WARNING! This program can confuse your I2C bus, cause data loss and worse!
I will probe file /dev/i2c-3, address 0x18, mode byte
Continue? [Y/n] Y
0 1 2 3 4 5 6 7 8 9 a b c d e f 0123456789abcdef
00: 01 00 00 00 00 00 00 00 00 00 00 10 08 08 00 00 ?..........???..
10: 1d 1d 40 40 00 00 00 00 00 00 00 00 00 00 00 00 ??@@............
20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
30: 00 00 00 00 40 00 40 00 00 40 00 5f 5f 00 00 00 ....@.@..@.__...
40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
70: 00 00 00 00 00 00 00 00 00 00 00 05 00 00 00 00 ...........?....
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
/data #

0 pdjuandi over 1 year ago in reply to Jalpan Parekh

TI__Mastermind 29755 points

Let's wait for Shenghao to review.

0 Shenghao Ding over 1 year ago in reply to Jalpan Parekh

TI__Genius 11640 points

Following ducuments at page 17, there's the register setting for headphone playback.

Design and Configuration Guide for the TLV320AIC3204 & TLV320AIC3254 Audio Codec

Is AVDD external or internal?

Page1Reg9 should be 0x3, but still 0.

Following kcontrol not set

SND_SOC_DAPM_PGA("HPL Power", AIC32X4_OUTPWRCTL, 5, 0, NULL, 0),

SND_SOC_DAPM_PGA("HPR Power", AIC32X4_OUTPWRCTL, 4, 0, NULL, 0),

0 Jalpan Parekh over 1 year ago in reply to Shenghao Ding

Prodigy 10 points

Hi,

Yes, AVDD is internal.

0 Jalpan Parekh over 1 year ago in reply to Shenghao Ding

Prodigy 10 points

I think Page1Reg9 should be 0x30. HPR/HPL Powered up (D4-D5 bits).

While playing audio Page1Reg9 set to 0x30 and then reset to 0x00.

Before playing the audio:

Page 0 registers:

0 1 2 3 4 5 6 7 8 9 a b c d e f 0123456789abcdef
00: 00 00 60 00 03 11 08 1b a2 00 00 08 02 00 80 02 ..`.?????..??.??
10: 00 08 08 02 80 01 00 04 00 00 01 00 00 01 04 00 .?????.?..?..??.
20: 00 00 00 00 44 00 00 00 00 00 00 00 00 00 00 00 ....D...........
30: 00 00 00 00 00 12 02 02 02 00 00 00 01 01 00 14 .....????...??.?
40: 0c 03 03 00 6f 38 00 00 00 00 00 ee 10 d8 7e e3 ???.o8.....???~?
50: 00 00 08 28 28 00 80 3e 3c 00 00 00 00 00 00 3e ..?((.?><......>
60: 3c 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 <...............
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................

Page 1 registers:

0 1 2 3 4 5 6 7 8 9 a b c d e f 0123456789abcdef
00: 01 00 00 00 00 00 00 00 00 00 00 10 08 08 00 00 ?..........???..
10: 13 13 40 40 00 00 00 00 00 00 00 00 00 00 00 00 ??@@............
20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
30: 00 00 00 00 40 00 40 00 00 40 00 5f 5f 00 00 00 ....@.@..@.__...
40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
70: 00 00 00 00 00 00 00 00 00 00 00 05 00 00 00 00 ...........?....
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................

-----------------------------------------------------------------------------------------------------------------------------------

While playing audio:

Page 0 registers:

0 1 2 3 4 5 6 7 8 9 a b c d e f 0123456789abcdef
00: 00 00 60 00 03 91 08 1b a2 00 00 88 82 00 80 02 ..`.?????..??.??
10: 00 08 88 82 80 01 00 04 00 00 01 00 00 01 84 00 .?????.?..?..??.
20: 00 00 00 00 44 aa 00 00 00 00 00 00 c0 00 00 00 ....D?......?...
30: 00 00 00 00 00 12 02 02 02 00 00 00 01 01 00 d4 .....????...??.?
40: 00 03 03 00 6f 38 00 00 00 00 00 ee 10 d8 7e e3 .??.o8.....???~?
50: 00 00 08 28 28 00 80 3e 3c 00 00 00 00 00 00 3e ..?((.?><......>
60: 3c 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 <...............
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................

Page 1 registers:
0 1 2 3 4 5 6 7 8 9 a b c d e f 0123456789abcdef
00: 01 00 00 00 00 00 00 00 00 30 00 10 08 08 00 00 ?........0.???..
10: 13 13 40 40 00 00 00 00 00 00 00 00 00 00 00 00 ??@@............
20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
30: 00 00 00 00 40 00 40 00 00 40 00 5f 5f 00 00 c0 ....@.@..@.__..?
40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
70: 00 00 00 00 00 00 00 00 00 00 00 05 00 00 00 00 ...........?....
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................

-----------------------------------------------------------------------------------------------------------------------------------

After playing the audio:

Page 0 registers:

Page 1 registers:

0 1 2 3 4 5 6 7 8 9 a b c d e f 0123456789abcdef
00: 01 00 00 00 00 00 00 00 00 00 00 10 08 08 00 00 ?..........???..
10: 13 13 40 40 00 00 00 00 00 00 00 00 00 00 00 00 ??@@............
20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
30: 00 00 00 00 40 00 40 00 00 40 00 5f 5f 00 00 00 ....@.@..@.__...
40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
70: 00 00 00 00 00 00 00 00 00 00 00 05 00 00 00 00 ...........?....
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................

0 pdjuandi over 1 year ago in reply to Jalpan Parekh

TI__Mastermind 29755 points

Somehow the path is disabled when audio is playing.

Not familiar with Linux so you will need to wait for Shenghao to comment.

0 Shenghao Ding over 1 year ago in reply to Jalpan Parekh

TI__Genius 11640 points

Not familiar Pulse Aduio arch, in alsa, after your settings, following route will be opened automatically.

Can you enable the debug flag for whole audio arch in kernel for more logs.

{"HPL Power", NULL, "HPL Output Mixer"},
{"HPL", NULL, "HPL Power"},

{"HPR Power", NULL, "HPR Output Mixer"},
{"HPR", NULL, "HPR Power"},

0 Jalpan Parekh over 1 year ago in reply to Shenghao Ding

Prodigy 10 points

Hi Shenghao,

I don't think that makes any issue. Because while playing audio HPL/HPR Power is turning on.

Yesterday I followed below document section 4.0.2. Manually set all the registers using i2cset command and it was working once. YES. I hear the audio.

TLV320AIC3204 Application Reference Guide

But when I have tried it again it is not working now. I am bit confused now. What is going wrong here.

I am definitely sure that, some mixer controls/registers need to be fine tune.

Could you please help me which are the basic controls/registers are needed to play audio on headphone (HPL and HPR).

Note: External supplies provided for LDOIN: 3.3V, DVDD/IOVDD: 1.8V, LDO_SELECT is grounded, MCLK external clock provided.

0 Jalpan Parekh over 1 year ago in reply to Shenghao Ding

Prodigy 10 points

Not familiar Pulse Aduio arch, in alsa, after your settings, following route will be opened automatically.

You mean to say Alsa changes the audio codec mixer controls?

I have observed some of the register values are changed while playing it. Like power control register, divider power control register, etc. In these registers power up bit set to 1 while playing audio.

0 Shenghao Ding over 1 year ago in reply to Jalpan Parekh

TI__Genius 11640 points

In TLV320AIC3204 Application Reference Guide, 4.0.3 offer the basic setting for headphone.

As to the register values has been changed, it seemed the issue.Kibndly check the log.

Is it possilbe the the headphone interrupt report the wrong message?

0 Jalpan Parekh over 1 year ago in reply to Shenghao Ding

Prodigy 10 points

Hi,

Kibndly check the log.

>> Logs doesn't show anything suspected.

Is it possilbe the the headphone interrupt report the wrong message?

>> As of now all the interrupts are disabled. I don't think so, interrupt makes issue.

Today I got the response from the Qualcomm side regarding the bits value get changed while playing audiio.

" For playback some registers will be updated corresponding to enabling/powering up the playback path at hw level, it is expected, "

I have followed 4.0.3 DAC Playback Through Class-D Headphone Amplifiers, but it couldn't help. Set the registers and playback.

./i2cset -fy 3 0x18 0x00 0x00; ./i2cset -fy 3 0x18 0x01 0x01; ./i2cset -fy 3 0x18 0x0B 0x81; ./i2cset -fy 3 0x18 0x0C 0x84; ./i2cset -fy 3 0x18 0x0D 0x00; ./i2cset -fy 3 0x18 0x0E 0x40; ./i2cset -fy 3 0x18 0x3C 0x08; ./i2cset -fy 3 0x18 0x00 0x01; ./i2cset -fy 3 0x18 0x01 0x00; ./i2cset -fy 3 0x18 0x02 0x00; ./i2cset -fy 3 0x18 0x7B 0x01; ./i2cset -fy 3 0x18 0x14 0x25; ./i2cset -fy 3 0x18 0x0A 0x00; ./i2cset -fy 3 0x18 0x0C 0x08; ./i2cset -fy 3 0x18 0x0D 0x08; ./i2cset -fy 3 0x18 0x10 0x00; ./i2cset -fy 3 0x18 0x11 0x00; ./i2cset -fy 3 0x18 0x09 0x30; ./i2cset -fy 3 0x18 0x00 0x00; ./i2cset -fy 3 0x18 0x3F 0xD4; ./i2cset -fy 3 0x18 0x40 0x00; ./i2cset -fy 3 0x18 0x00 0x01; ./i2cset -fy 3 0x18 0x03 0xC0; ./i2cset -fy 3 0x18 0x04 0xC0;

PAGE0:

0 1 2 3 4 5 6 7 8 9 a b c d e f 0123456789abcdef
00: 00 00 60 00 00 11 04 00 00 00 00 81 84 00 80 02 ..`..??....??.??
10: 00 08 01 01 80 01 00 04 00 00 01 00 00 00 04 00 .?????.?..?...?.
20: 00 00 00 00 00 aa 11 00 00 00 00 00 00 00 80 00 .....??.......?.
30: 00 00 00 00 00 12 03 02 02 00 00 00 01 01 00 d4 .....????...??.?
40: 00 00 00 00 6f 38 00 00 00 00 00 ee 10 d8 7e e3 ....o8.....???~?
50: 00 00 88 00 00 00 00 00 7f 00 00 00 00 00 00 00 ..?.....?.......
60: 7f 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ?...............
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................

PAGE1:
0 1 2 3 4 5 6 7 8 9 a b c d e f 0123456789abcdef
00: 01 00 00 c0 c0 00 00 00 00 30 00 10 08 08 00 00 ?..??....0.???..
10: 00 00 40 40 25 00 00 00 00 00 00 00 00 00 00 00 ..@@%...........
20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
30: 00 00 00 00 00 00 00 00 00 00 00 80 80 00 00 c0 ...........??..?
40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
70: 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 00 ...........?....
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................

I have verified all registers value as per 4.0.3 section while playing audio. Which register values you think it is wrong while playing audio. Could you please point out the registers.

Note: I have set Page1Register1 value set to 0x00 as AVDD is grounded in our case.

Please also suggest if we can debug anything from hardware side.

0 Shenghao Ding over 1 year ago in reply to Jalpan Parekh

TI__Genius 11640 points

add following commands, at the end of your script

./i2cset -fy 3 0x18 0x00 0x01
./i2cset -fy 3 0x18 0x09 0xc0

0 Jalpan Parekh over 1 year ago in reply to Shenghao Ding

Prodigy 10 points

Then Page1Register9 remain 0x00 while playing audio.

0 Shenghao Ding over 1 year ago in reply to Jalpan Parekh

TI__Genius 11640 points

So, currently can you hear the sound from headphone?

0 Jalpan Parekh over 1 year ago in reply to Shenghao Ding

Prodigy 10 points

0 Jalpan Parekh over 1 year ago in reply to Shenghao Ding

Prodigy 10 points

Hi,

How can we debug further? Please suggest.

0 Shenghao Ding over 1 year ago in reply to Jalpan Parekh

TI__Genius 11640 points

Let me consult our codec expert on this issue.

0 Jalpan Parekh over 1 year ago in reply to Shenghao Ding

Prodigy 10 points

Sure.

0 pdjuandi over 1 year ago in reply to Jalpan Parekh

TI__Mastermind 29755 points

So do we know why the registers setting was reconfigured to disable the audio path when playing?

The audio path of interest must be enabled otherwise you will not hear any sound.

0 Shenghao Ding over 1 year ago in reply to Jalpan Parekh

TI__Genius 11640 points

const struct regmap_config aic32x4_regmap_config = {
	.max_register = AIC32X4_REFPOWERUP,
	.ranges = aic32x4_regmap_pages,
	.cache_type = REGCACHE_NONE,
	.num_ranges = ARRAY_SIZE(aic32x4_regmap_pages),
};
EXPORT_SYMBOL(aic32x4_regmap_config);

Try REGCAHE_NONE, and set the register and dump the register again.

0 Jalpan Parekh over 1 year ago in reply to Shenghao Ding

Prodigy 10 points

Not able to hear the audio.

PAGE0:

0 1 2 3 4 5 6 7 8 9 a b c d e f 0123456789abcdef
00: 00 00 60 00 00 11 04 00 00 00 00 81 84 00 80 02 ..`..??....??.??
10: 00 08 01 01 80 01 00 04 00 00 01 00 00 00 04 00 .?????.?..?...?.
20: 00 00 00 00 88 aa 11 00 00 00 00 00 00 00 00 00 ....???.........
30: 00 00 00 00 00 12 02 02 02 00 00 00 01 01 00 d4 .....????...??.?
40: 00 00 00 00 6f 38 00 00 00 00 00 ee 10 d8 7e e3 ....o8.....???~?
50: 00 00 88 00 00 00 00 00 7f 00 00 00 00 00 00 00 ..?.....?.......
60: 7f 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ?...............
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................

PAGE1:

0 1 2 3 4 5 6 7 8 9 a b c d e f 0123456789abcdef
00: 01 00 00 c0 c0 00 00 00 00 30 00 10 08 08 00 00 ?..??....0.???..
10: 00 00 40 40 25 00 00 00 00 00 00 00 00 00 00 00 ..@@%...........
20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
30: 00 00 00 00 00 00 00 00 00 00 00 80 80 00 03 c0 ...........??.??
40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
70: 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 00 ...........?....
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................

0 Jalpan Parekh over 1 year ago in reply to pdjuandi

Prodigy 10 points

Which register you are talking about?

I got below answer from Qualcomm:

" For playback some registers will be updated corresponding to enabling/powering up the playback path at hw level, it is expected, "

0 Shenghao Ding over 1 year ago in reply to Jalpan Parekh

TI__Genius 11640 points

const struct regmap_config aic32x4_regmap_config = {
.max_register = AIC32X4_REFPOWERUP,
.ranges = aic32x4_regmap_pages,
.cache_type = REGCACHE_NONE,
.num_ranges = ARRAY_SIZE(aic32x4_regmap_pages),
};
EXPORT_SYMBOL(aic32x4_regmap_config);

Try REGCAHE_NONE, and set the register and dump the register again.

0 Jalpan Parekh over 1 year ago in reply to Shenghao Ding

Prodigy 10 points

Yes, after making these changes I tried to play and dump registers.

0 Jalpan Parekh over 1 year ago in reply to Jalpan Parekh

Prodigy 10 points

Hi Shenghao Ding

We have given MCLK using external crystal. Is it possible to have synchronization issue?

0 pdjuandi over 1 year ago in reply to Jalpan Parekh

TI__Mastermind 29755 points

Looking at your registers above; see attached with my comment, I noticed the following:

Your clock settings are for 22.1KHz fs and PLL is disabled.
Your HP power is from AVDD, but AVDD LDO is powered down.

Fullscreen 8863.register.txt Download

PAGE0:

0 1 2 3 4 5 6 7 8 9 a b c d e f 0123456789abcdef`	Comment
00: 00 00 60 00 00 11 04 00 00 00 00 81 84 00 80 02 	MCLK to PLL and CODEC_CLKIN, PLL powered down, NDAC=1 powered up, MDAC=4 powered up, DOSR=128
10: 00 08 01 01 80 01 00 04 00 00 01 00 00 00 04 00 	NADC/MADC powered down, Slave mode I2S, 16-bit
20: 00 00 00 00 88 aa 11 00 00 00 00 00 00 00 00 00 
30: 00 00 00 00 00 12 02 02 02 00 00 00 01 01 00 d4 	Left and right DAC powered up
40: 00 00 00 00 6f 38 00 00 00 00 00 ee 10 d8 7e e3 	Left and right DAC not muted
50: 00 00 88 00 00 00 00 00 7f 00 00 00 00 00 00 00 	ADC powered down
60: 7f 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................

PAGE1:

0 1 2 3 4 5 6 7 8 9 a b c d e f 0123456789abcdef
00: 01 00 00 c0 c0 00 00 00 00 30 00 10 08 08 00 00 	Analog block enabled, AVDD LDO powered down, HPL=ClassD powered up with AVDD, Left DAC+=HPL, Right DAC+=HPR
10: 00 00 40 40 25 00 00 00 00 00 00 00 00 00 00 00 	HPL and HPR not muted
20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
30: 00 00 00 00 00 00 00 00 00 00 00 80 80 00 03 c0 
40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
70: 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 00 ...........?....
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................

My suggestion:

Enable AVDD LDO.
With 11.2896MHz MCLK, use 44.1KHz Fs by using the setting below without PLL first.
If you need 48KHz then enable PLL and configure the PLL ratio to get 48KHz fs.
You can download the PLL clock from TLV320AIC3204 data sheet, product information and support | TI.com under SLAR163

Regards

0 Jalpan Parekh over 1 year ago in reply to pdjuandi

Prodigy 10 points

Hi pdjuandi

Thanks for pointing out the issue. In our case we do not use AVDD LDO. We use LDOIN supply for Headphone.

After changing the P1_R10_D1 Bit to 1 (powered with LDOIN supply), I can hear the audio on headphone.

Note: While starting audio I hear some noise once and then it starts playing audio.

Last help require from your end, as of now I have set register manually using i2cset, so which mixer controls commands I can use which replicate the same functionality?

Audio

Audio forum

TLV320AIC3204: Not able to play/capture audio on headphone