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TAS2505: "LDO Control" Register marked as a "reserved register" in datasheet

Sigurd Baardsen
Prodigy 30 points

Part Number: TAS2505

The "LDO Control" Register has become a "reserved register" in newer TAS2505 datasheets. Can we still rely on writing and reading from the "LDO Control" Register? Or is this now considered undefined behavior? 

Will for example the "LDO Select" bit (D0) still have the correct value? Same with writing to the various relevant bits in the register? 

  • 0
    TI__Guru** 114535 points

    Hi Sigurd,

    The LDO should not be used on this device, thus we removed the LDO block from the device diagrams, ask to short LDO_SEL pin to GND and show the LDO related registers as reserved. Although the registers are still active.
    This feature will be added back in a few more months.

    Best regards,
    -Ivan Salazar
    Applications Engineer

  • 0 in reply to Ivan Salazar
    Prodigy 30 points

    Hi,

    Thanks for your reply. To clarify, we fixed the TAS2505 issue in a new revision of the PCBA. We will however have both the old PCBA and the fixed one in the market. Thus we need to check (in firmware) which version it is, so we can configure the registers accordingly.

    The new PCBA will have the LDO_SEL pin set to GND, and the old one will not. Reading the "LDO Select" bit from the "LDO Control" register should provide us with the information we need. The question is, can we trust that it will?

  • 0 in reply to Sigurd Baardsen
    TI__Guru** 114535 points

    Hi Sigurd,

    So your question is if the register bit that reads the state of LDO_SEL pin is accurate?
    This bit is functional so it should still read the correct value.

    Best regards,
    -Ivan Salazar
    Applications Engineer

  • 0 in reply to Ivan Salazar
    Prodigy 30 points

    OK, thanks.

    As for writing, this is from the "TAS2505 Application Reference Guide":
    "At powerup, PLL and HP Level Shifters powered down to save leakage current issue when DVDD is powered up and AVDD is powered down. This powered down must be powered up by writing Page 1, Reg 2, D3 = 0 at the time AVDD is applied, either from internal LDO or through external LDO."

    This bit is also in the "LDO Control" register. So this should also still be written to, for both old and fixed PCBA (i.e. with external LDO)?

  • 0 in reply to Sigurd Baardsen
    TI__Guru** 114535 points

    Hi Sigurd,

    That is correct, bit 3 from page 1 register 2 is still valid and should be written accordingly.

    Best regards,
    -Ivan Salazar
    Applications Engineer

  • 0 in reply to Ivan Salazar
    Prodigy 30 points

    Thanks!

    Last question, what about "Master Reference enabled", in the "REF, POR and LDO BGAP Control" register? In the old PCBA (using the internal LDO), this is enabled. Should it be disabled when using external LDO (new PCBA)?

    Couldn't really find any detailed information about this.

  • +1 in reply to Sigurd Baardsen
    TI__Guru** 114535 points

    Hi Sigurd,

    You should follow the instructions provided for the case of not using the internal LDO, specifically for shutdown it's section 3.8.1.2.2. Basically, you can power down the LDO bandgap as the LDO is not being used.

    Best regards,
    -Ivan Salazar
    Applications Engineer