• State TI Thinks Resolved
  • Locked Locked
  • Replies 8 replies
  • Answers 2 answers
  • Subscribers 29 subscribers
  • Views 404 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

PCM5122: PCM5122 uncommon audio clock configuration

chris turner
Prodigy 10 points
Part Number: PCM5122
Other Parts Discussed in Thread: , PCM5101

We are trying to run the PCM5122 with a sample frequency of 256kHz and a SCK/BCK of 16.384MHz.

We are running in SPI mode and see no output despite configuring all of the registers correctly (we think)
When going through the datasheet we are curious whether or not a sample frequency of 256kHz is even allowed for this device, given that some of the specs say “up to 384kHz” but then others specifically omit frequencies between 192kHz and 384kHz.

  • 0
    TI__Mastermind 26240 points

    Hi Chris, I will be in office Tuesday (tomorrow)  and will take a look at this then.

    regards,

    Arash

  • 0 in reply to Arash Loloee
    Prodigy 10 points

    Arash, here is our register dump.

  • 0 in reply to chris turner
    TI__Mastermind 26240 points

    Hi Chris,

    In theory the DAC can work at LRCLK of 256K but since this is an audio DAC, its performance at non-audio sampling rates might be not similar to what is shown in datasheet. 

    Table 32. System Master Clock Inputs for Audio Related Clocks  and SCK rates that are not common to standard audio clocks are only supported in software mode by configuring various PLL and clock-divider registers. The register dump has many x00 readings so I would suggest to refer to fig 63 of datasheet to see the datasheet and track the various registers that need to be set. Also please refer to example shown in  section 8.3.6.5 PLL Calculation. sectrion  8.3.6.4 Clock Generation Using the PLL has  table 34 for appropriate registers for the above calculations .

    Here is a sample code to be used as example:

    # PLLCK = CLKIN x R x (J.D) / P = 11.3MHz x 1 x 8 / 1 = 90.316 MHz
    # PLL clock source = SCK
    w E0 0D 00
    # P = 1
    w E0 14 00
    # J = 8
    w E0 15 08
    # Decimal value = 0
    # R = 0
    w E0 18 00

    #DSP CLK = PLLCLK/DDSP = 90.316 MHz /2 = 45.15 MHz
    # division by 2
    w E0 1B 01
    # DAC CLK = PLLCK/DDAC = 90.3168 / 16 = 5.6448MHz
    # Division by 16
    w E0 1C 0F
    # CP(charge pump) Clock = DAC CLK / NCP = 5.6448MHz / 4 = 1.4112MHz
    # Division by 4
    w E0 1D 03
    # Oversampling Ratio clock = DAC CLK /DOSR = 5.64MHz / 8 = 705.6KHz
    # Division by 8
    w E0 1E 07

    I would check few things, even before checking the registers. These are the basic steps to debug that needs to be 

    1-Make sure device is not muted by monitoring XSMT pin of the DAC.

    2-Plot all the waveforms of the clocks and data . It is very critical that your selected data format matches with the appropriate diagram in figures 13-16 in section 8.3.2.2 PCM Audio Data Formats .

    3-And finally, if possible test the DAC with a supported audio LRCLK  before activating the PLL. In hardwired mode, the internal PLL is disabled as soon as an external SCK is supplied.

    I think once you follow these steps you can set it up correctly.

    Regards,

    Arash

  • 0 in reply to Arash Loloee
    Prodigy 10 points

    Here are some additional questions from our side:

    Pll will be disabled.  SDAC mux will select SCK as input, which is 16.384 MHz.  SCL/PLL mux will select SCK as source.  What divider should we have for the DSPCK (register 27).  What divider should we have for DACCK (register 28).  and what dividers for CPCK (reg 29) and DOSR (register 30) and OSRCK mux?  We drive a 256KHz LRCK to the device, and a 16 MHz (64X clock, 2 x 32-bit data will be shifted in) to the BCK clock input.  So we don't really care about PLL settings, so those are off the table

  • 0 in reply to chris turner
    TI__Mastermind 26240 points

    Chris,

    If you have a non-audio application probably it is better to use one of our  non-audio DACs. I have used these DACs in audio specific sampling rates.

    This part requires a system clock to operate the digital interpolation filters and advanced segment DAC
    modulators. The system clock detection circuitry  automatically senses the system-clock frequency but fir non-audio it can not do it , so you have to activate the PLL to generate the appropriate SCK .   May be you can target a 128xfs for SCK .

    I provided an example above, you can use that example and adjust the values .

    Regards,

    Arash

  • 0 in reply to Arash Loloee
    Prodigy 10 points

    Arash,

    We purchased the eval board PCM5122EVM-U  as a reference.

    We are having difficulty even getting the Eval board to be recognized by Windows 11.

    We downloaded the CC PCM5101 Demo software (supposed to be compatable with the PCM5122)

    When we run the Demo software the software consistently gives an "EVM Status: Communications Error"

    Since this eval board uses the TAS1020B USBStreamingController, I assume we need the Windows 11 drivers for that controller.

    So far we have been unable to locate drivers for the TAS1020B - one forum post I saw said that "TAS1020B is no longer supported"

    Any help here getting this up and running would be greatly appreciated.

  • 0 in reply to chris turner
    Prodigy 10 points

    Arash, exciting news we were able to get our original board with the PCM5122!  We changed The register at 0X1C (DACLK) should be to 0x40