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SRC4184: SRC4184IPAGT and CDCE913PW

user6308822
Prodigy 70 points
Part Number: SRC4184

Hello,Team,

 

I have questions about SRC4184IPAGT and CDCE913PW

 

・SRC4184IPAGT
Q1
Are there any AC Operating Conditions which is related with RCKI,
for example, setup,hold and synchronization with BCKI/O,LRCKI/O,TDMIand so on.
Q2
According to Figure17 in datasheet,i can see RCKI signal are inputed to each devices(SRC4184)which is controlled in slave mode from 1 clock generator which devide the line to 3 lines.
Should i devide clock signal from 1 clock generator? I mean, should i use RCKI to each devices  in sysnc?
for example, in case using CDCE913PW for clock generator,CDCE913PW output CLK which is made from the same Pdiv1 and connect such as "Y1-SRC1/Y2-SRC2/Y3-SRC3",are there any problems?

 

・CDCE913PW
Q1
Is there any latency between Y1 to Y2/Y3, when this devide is set to use Y1,Y2,Y3 from Pdiv1?
Q2
Why is there difference about M,N,freq for PLL,in Clock Pro between when using only Y1 and when using Y1/Y2/Y3,in spite of using the same Inclock and the same out Freq setting.
I guess there is no change to set Y2/Y3 to use from Pdiv1 which is used for Y1 setting.
Anyway, in this case that this device to use  Y1/Y2/Y3 the same freq and the same Pdiv,i can use reg setting refer to BitViewer in Clock Pro,is that OK?
Q3
In Clock Pro, why i cannot see reg15 nad 31 in BitViewer?
Q4
If i set reg"EEWRITE" to 1 for save the data to memory, is reg"EELOCK" set to 1 immediately without operating reg"EELOCK" setting?

 

 

Thank you for your support

  • 0
    TI__Mastermind 23920 points

    Hello,

    Questions regarding SRC:

    There is no AC operating conditions related to RCKI. In fact the only requirements  are described in Figure 2. ( Reference Clock Input Connections and Timing Requirements).

    The reference clk in figure 17  is distributed from an external source to all slave devices in a daisy chain configuration , so reference clk is distributed from same source and thus should be in sync. 

    questions regarding CDCE913PW:

    Another team handles questions related to CDCE913PW . Please create a new E2E thread  regarding CDCE913PW  (mention it in your title)  and post your question in the new E2E post so it goes to the correct team. 

    Regards,

    Arash

  • 0 in reply to Arash Loloee
    Prodigy 70 points

    Hello,Team,

    Thank you for your replying.

    ex Q1
    Should i input RCKI as SYNC both of Group A and B?
    is that no need to input RCKI as SYNC to Group A and B?

    ex Q2
    >>The reference clk in figure 17 is distributed from an external source to all slave devices in a daisy chain configuration , so reference clk is distributed from same source and thus should be in sync.
    Can i get data of margin as SYNC of RCKI?

    Thank you for your kindness

  • 0 in reply to user6308822
    TI__Mastermind 23920 points

    Hello,

    I am not sure  about the schematic that your are refering to. But RCKI is a reference clk which is additional to LRCLK;  and what you are calling SYN probably is the LRCLK from another device. If this is what you mean they FSYNC/LRCLK are different from RCKI  and you can not connect them.

    Please refer to  Figure 14. to see a sample connection.

    Regards,

    Arash

  • 0 in reply to Arash Loloee
    Prodigy 70 points

    Hello,Team,
    Thank you for your replying.

    I guess you do not det it what i mean.
    ～Q～
    There are 2group A and B in 1 device, according to attachment i add.
    So,should i input RCKIA and RCKIB as SYNC?
    or i can use RCKIA which is not SYNC with RCKIB?


    And the red line(RCKI) which is RCKI, is there any tolerance of SYNC btw each devices RCKI?

    Thank you for your kindness

  • 0 in reply to user6308822
    TI__Mastermind 23920 points

    Hello , Please refer to  functional block diagram of the SRC4184.  As you can see, the SRC4184 is segmented into two stereo SRC sections, referred to as SRC A and SRC B. Each section can operate independently from the other. Each section has individual sets of configuration pins in Hardware mode, and separate banks of control and status registers in Software mode.

    Regards,

    Arash

  • 0 in reply to Arash Loloee
    Prodigy 70 points

    Hello,Team,
    Thank you for your replying.

    I guess you miss that i questioned you below.

    And the red line(RCKI) which is RCKI, is there any tolerance of SYNC btw each devices for RCKI that is from the same Clock Generator?

    Thank you for your kindness.

  • 0 in reply to user6308822
    TI__Mastermind 23920 points

    Sorry I missed to mention that since it is not mentioned in the  datasheet, I can not give you any suggestion for the tolerance.

    Regards,

    Arash