TLV320ADC5140: AGND and DGND

Hideki Hayashi1

Part Number: TLV320ADC5140

Hi team,

Looking at the connection example described in the specification, the GND of ADC5140 is connected only to the AGND (the ▼ mark in the figure below).

DGND is connected to the DREG and IOVDD through a bypass capacitor.

Although the AGND and DGND of the customer schematic are separated, is it desirable to connect the AGND and DGND at a single point close to the the chip? Or is it better not to separate?

This is because the noise superposition via GND originating from the I2S line with the master device is an issue, and it is assumed that this IC is caused by a small potential difference between analogue ground and digital ground at the digital ground.

Could you please tell us about the GND routing?

Best regards,

Hayashi

over 1 year ago

+1 Sanjay Dixit over 1 year ago

TI__Mastermind 23030 points

The Vref and MicBias capacitors must be direct connected to the AVSS point on the IC.

We should make a ground plane that runs through the centre of the IC. All grounds related to the chip must return to this ground point/

0 Hideki Hayashi1 over 1 year ago in reply to Sanjay Dixit

TI__Expert 8440 points

Hi Sanjay,

Customer don't use MicBias. Should it be open or connected to ground via caps?

Sanjay Dixit said:
through the centre of the IC

Does it mean Themal Pad (VSS)?

When the DGND and AGND are separated as shown in the figure below, should the GND connection point shown in the lower left be placed close to the IC to minimize closed circuit design?