TLV320ADC6140: DRE causing distortion with default settings

Chandler McCowan

Part Number: TLV320ADC6140

Hello!

I am currently bringing up a prototype that has the TLV320ADC6140 for some line input audio and outputting on TDM.

The differential audio is AC coupled to the ADC and below are the I2C settings configured at startup:

// Wake from Sleep and use internal AREG
TLV320ADC_I2C_REG_SLEEP_CFG = 0b10000001;

// configure channel 1 as line input and enable DRE
TLV320ADC_I2C_REG_CH1_CFG0 = 0b10000001;

// Enable Channel 1 Serial Output
TLV320ADC_I2C_REG_ASI_OUT_CH_EN = 0b10000000;

// Power up ADC and PLL
TLV320ADC_I2C_REG_PWR_CFG = 0b11100000;

// Endless loop
while(TRUE){
    pollStatusRegisters();
    delay(LOOP_DELAY);
};

For testing, I have an Audio Precision APx555 being used as the input signal generator, and as the TDM Receiver. My device under test is acting as the TDM slave device, while the AP is set as Master.

Generator is set to 1kHz Sine Wave adjusting level until hitting 0 dB_FS(~1.93 V_RMS)

Unfortunately, when enabling DRE with default settings, there is some distortion seen on the waveform.

Disabling DRE removes these distortions and THD+N is measured to be -92.18 dB

I've read through the DRE application note (SBAA400A – SEPTEMBER 2019 – REVISED DECEMBER 2023) and could not find anything to point towards what might be causing this issue.

The sampling rate was set to 96kHz

Any ideas on what I might be doing wrong? Thanks in advance!

11 months ago

0 Dejan Micic 11 months ago

Prodigy 50 points

Have you played around with the maximum gain setting trying to lower it?

0 Chandler McCowan 11 months ago in reply to Dejan Micic

Prodigy 15 points

I have tried to adjust the gain settings for DRE with no impact on signal quality. From my understanding of the DRE feature, it shouldn't be engaged at the signal levels I was testing. As signal level decreases, DRE will begin to increase gain and should be adjusted to prevent clipping at your expected low signal levels that are desired to be amplified.

At 1.93 V_RMS, the DRE should be disengaged and not impacting the signal quality?

0 Sanjay Dixit 11 months ago in reply to Chandler McCowan

TI__Mastermind 23030 points

Have you enabled DRE in the DSP_CFG1 Register?

0 Chandler McCowan 11 months ago in reply to Sanjay Dixit

Prodigy 15 points

Hey Sanjay, thank for replying

DRE is set as default option on reset, and I also have checked the register and ensured that DRE is selected

0 Chandler McCowan 11 months ago

Prodigy 15 points

I have managed to show that the distortions are dependent on Sample Rate. Reducing the sampling rate form 96kHz to 48kHz while still having DRE enabled shows promising results. Looking at Table 2-12 of the DRE application note mentioned in the original post, the sampling rate of 96kHz should be supported for the one channel I am testing now.

Have I not only one channel enabled from the settings mentioned above?

I have also been unable to see the DRE functionality be triggered, I have brought the input level down to -65 with no apparent gain being applied

0 Sanjay Dixit 11 months ago in reply to Chandler McCowan

TI__Mastermind 23030 points

I shall respond back tomorrow.

0 Sanjay Dixit 10 months ago in reply to Sanjay Dixit

TI__Mastermind 23030 points

Have you tried measuring SNR with DRE on and off.?

0 Chandler McCowan 10 months ago

Prodigy 15 points

Thanks for the replies! I managed to solve the issue of distortions when running DRE.

Channels 1-4 are enabled by default, in the IN_CH_EN Register

I disabled channels 2-4 and was able to achieve good signal quality at a sampling rate of 192kHz

I had missed this register, believing that enabling the serial output is what enables the channels themselves.

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TLV320ADC6140: DRE causing distortion with default settings