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TAS2563: No audio played

Part Number: TAS2563

Hello

I have been trying to get our AMP to work with our design, but to no avail. I started with testing on the development board, and got both an I2C driver and an I2S driver up and running where I could play audio just fine. But for some reason I cannot get it to work with our integrated desing. It is run on an ESP32S which is the same as the one used when testing the development board.

Here is the schematic used for the TAS amp


And here is the current version of the configuration sequence

const cfg_reg device_configuration_sequence[] = {
{0x00, 0x00},
{0x7F, 0x00},
{0x01, 0x01},
{0x00, 0x00},
{0x7F, 0x00},
{0x00, 0xFD},
{0x0D, 0x0D},
{0x3A, 0x64},
{0x3B, 0x64},
{0x00, 0x00},
{0x7F, 0x00},
{0x00, 0x00},
{0x02, 0x02},
{0x03, 0x28},
{0x04, 0xCE},
{0x05, 0xA2},
{0x06, 0x49},
{0x07, 0x02},
{0x08, 0x70},
{0x11, 0x7f},
{0x09, 0x10},
{0x0A, 0x03},
{0x0B, 0x44},
{0x0C, 0x40},
{0x0D, 0x04},
{0x0E, 0x05},
{0x0F, 0x06},
{0x10, 0x07},
{0x12, 0x12},
{0x13, 0x76},
{0x14, 0x01},
{0x15, 0x2E},
{0x1A, 0xFC},
{0x1B, 0xA6},
{0x1C, 0xDF},
{0x1D, 0xFF},
{0x30, 0x19},
{0x31, 0x40},
{0x32, 0x80},
{0x33, 0xB4},
{0x34, 0x4B},
{0x35, 0xA4},
{0x38, 0x09},
{0x3B, 0x58},
{0x3C, 0x54},
{0x3D, 0x08},
{0x3E, 0x10},
{0x3F, 0x00},
{0x40, 0x77},
{0x41, 0x41},
{0x42, 0x00},
{0x00, 0x00},
{0x7F, 0x00},
{0x00, 0x01},
{0x08, 0x40},
{0x00, 0x00},
{0x7F, 0x00},
{0x00, 0x02},
{CFG_META_BURST,4},
{0x0C, 0x40},
{0x00, 0x00},
{0x00, 0x00},
{0x00, 0x00},
{0x7F, 0x00},
{0x00, 0x02},
{CFG_META_BURST,4},
{0x10, 0x7C},
{0xB5, 0xAE},
{0x94,0x00},
{0x00, 0x00},
{0x7F, 0x00},
{0x00, 0x04},
{CFG_META_BURST,12},
{0x74, 0x7F},
{0xFB, 0xB6},
{0x14, 0x80},
{0x04, 0x49},
{0xED, 0x7F},
{0xF7, 0x6C},
{0x28,0x00},
{0x00, 0x00},
{0x7F, 0x00},
{0x00, 0x02},
{CFG_META_BURST,12},
{0x68, 0x7F},
{0xFB, 0xB6},
{0x14, 0x80},
{0x04, 0x49},
{0xED, 0x7F},
{0xF7, 0x6C},
{0x28, 0x00},
{0x00, 0x00},
{0x7F, 0x00},
{0x00, 0x02},
{CFG_META_BURST,4},
{0x14, 0x2D},
{0x6A, 0x86},
{0x6F, 0x00},
{0x00, 0x00},
{0x7F, 0x00},
{0x00, 0x02},
{0x18, 0x47},
{0x5C, 0x28},
{0xF6, 0x00},
{0x00, 0x00},
{0x7F, 0x00},
{0x00, 0x02},
{CFG_META_BURST,4},
{0x1C, 0x16},
{0x66, 0x66},
{0x66,0x00},
{0x00, 0x00},
{0x7F, 0x00},
{0x00, 0x02},
{CFG_META_BURST,4},
{0x20, 0x1A},
{0x66, 0x66},
{0x66,0x00},
{0x00, 0x00},
{0x7F, 0x00},
{0x00, 0x02},
{CFG_META_BURST,4},
{0x24, 0x08},
{0x00, 0x00},
{0x00,0x00},
{0x00, 0x00},
{0x7F, 0x00},
{0x00, 0x02},
{CFG_META_BURST,4},
{0x28, 0x17},
{0x33, 0x33},
{0x33,0x00},
{0x00, 0x00},
{0x7F, 0x00},
{0x00, 0x02},
{CFG_META_BURST,4},
{0x2C, 0x15},
{0x99, 0x99},
{0x9A,0x00},
{0x00, 0x00},
{0x7F, 0x00},
{0x00, 0x05},
{CFG_META_BURST,4},
{0x24, 0x7F},
{0xFE, 0xFD},
{0x47,0x00},
{0x00, 0x00},
{0x7F, 0x00},
{0x00, 0x05},
{CFG_META_BURST,4},
{0x2C, 0xFE},
{0xFE, 0xA4},
{0xB5,0x00},
{0x00, 0x00},
{0x7F, 0x00},
{0x00, 0x05},
{CFG_META_BURST,4},
{0x40, 0x00},
{0x00, 0x03},
{0x20,0x00},
{0x00, 0x00},
{0x7F, 0x00},
{0x00, 0x05},
{CFG_META_BURST,4},
{0x44, 0x02},
{0x46, 0xB4},
{0xE4,0x00},
{0x00, 0x00},
{0x7F, 0x00},
{0x00, 0x05},
{CFG_META_BURST,4},
{0x1C, 0x01},
{0xC9, 0x24},
{0x92,0x00},
{0x00, 0x00},
{0x7F, 0x00},
{0x00, 0x05},
{CFG_META_BURST,4},
{0x20, 0x00},
{0x12, 0x49},
{0x25,0x00},
{0x00, 0x00},
{0x7F, 0x00},
{0x00, 0x02},
{CFG_META_BURST,4},
{0x5C, 0x00},
{0x01, 0x09},
{0x45,0x00},
{0x00, 0x00},
{0x7F, 0x00},
{0x00, 0x02},
{CFG_META_BURST,4},
{0x64, 0x00},
{0x00, 0x12},
{0xC0,0x00},
{0x00, 0x00},
{0x7F, 0x00},
{0x00, 0x04},
{CFG_META_BURST,4},
{0x60, 0x04},
{0xCC, 0xCC},
{0xCD,0x00},
{0x00, 0x00},
{0x7F, 0x00},
{0x00, 0x04},
{CFG_META_BURST,4},
{0x64, 0x00},
{0x00, 0x00},
{0x00,0x00},
{0x00, 0x00},
{0x7F, 0x00},
{0x00, 0x04},
{CFG_META_BURST,4},
{0x38, 0x00},
{0x3C, 0xCF},
{0x7A,0x00},
{0x00, 0x00},
{0x7F, 0x00},
{0x00, 0x04},
{CFG_META_BURST,4},
{0x40, 0x00},
{0x40, 0xFE},
{0x54,0x00},
{0x00, 0x00},
{0x7F, 0x00},
{0x00, 0x04},
{CFG_META_BURST,4},
{0x5C, 0x04},
{0xCC, 0xCC},
{0xCD,0x00},
{0x00, 0x00},
{0x7F, 0x00},
{0x00, 0x04},
{CFG_META_BURST,4},
{0x4C, 0x00},
{0x00, 0x00},
{0x00, 0x00},
{0x00, 0x00},
{0x7F, 0x00},
{0x00, 0x04},
{CFG_META_BURST,4},
{0x54, 0x17},
{0x99, 0x99},
{0x9A,0x00},
{0x00, 0x00},
{0x7F, 0x00},
{0x00, 0x04},
{CFG_META_BURST,4},
{0x6C, 0x00},
{0x00, 0x00},
{0x27,0x00},
{0x00, 0x00},
{0x7F, 0x00},
{0x00, 0x03},
{CFG_META_BURST,4},
{0x24, 0x39},
{0x80, 0x00},
{0x00,0x00},
{0x00, 0x00},
{0x7F, 0x00},
{0x00, 0x03},
{CFG_META_BURST,4},
{0x18, 0x72},
{0x14, 0x82},
{0xC0,0x00},
{0x00, 0x00},
{0x7F, 0x00},
{0x00, 0x03},
{CFG_META_BURST,4},
{0x1C, 0x00},
{0x00, 0x00},
{0x64,0x00},
{0x00, 0x00},
{0x7F, 0x00},
{0x00, 0x03},
{CFG_META_BURST,4},
{0x20, 0x40},
{0xBD, 0xB7},
{0xC0,0x00},
{0x00, 0x00},
{0x7F, 0x00},
{0x00, 0x03},
{CFG_META_BURST,4},
{0x28, 0x2D},
{0x6A, 0x86},
{0x6F, 0x00},
{0x00, 0x00},
{0x7F, 0x00},
{0x00, 0x00},
{0x30, 0x19},
{0x00, 0x00},
{0x7F, 0x00},
{0x00, 0x00},
{0x02, 0x00},
};

During the meta_burst section I of course read the next first hex as the address followed by the next X hex as the value to write, with X being given from {CFG_META_BURST,X}

Can anyone spot what is wrong? I read the live interrupts and there is no issues. The I2S is configured to have a sample rate of 48000, left justified, 1 channel and 16 bits per sample, and the I2C clockfrequency is 
100000 hZ
  • Hi Christoffer,

    Can you confirm the device is acking all the I2C commands? I noticed ADDR pin C4 floating. Just to double check this, you can replace the I2C address from whatever you're using to 0x48 (7-bit) / 0x90 (8-bit).

    Regarding the audio format, you mentioned 1 channel, but you still have 2 channels with one of them empty, is that correct? I2S is a stereo format, FSYNC is low for first half of the sample and high for the second half. You may share scope captures of the clocks for a whole sample.

    Also please read the latched interrupts rather than live, these are located in page 0 reg 0x24 through 0x27.

    Best regards,
    -Ivan Salazar
    Applications Engineer

  • Hi Ivan

    Thank you very much for the quick response, regarding your follow up questions

    1) From what I can tell It does respond rather well to the I2C commands. I use the 7-bit 0x48 address and get no error message. Also if I write {0x02,0x00} and read the register of 0x02 it does give 0x00 and if I write {0x02,0x03} it also gives 0x03 when reading the register.

    2) For the I2S it should put the audio into both the left and right channels. When testing the setup with the development board it worked fine and when we used the previous ampthe TS2110 it also worked. Here is a picture of the output FSYNC when audio should be played scoped via analog discovery 2

    3) Here is the values from the latched interupt:

    {0x24, 0x04}

    {0x25, 0x00}

    {0x26, 0x11}

    {0x27, 0x80}

    {0x28, 0x00}

    {0x29, 0x40}

  • Hello again!

    Regarding nr 2, I am sorry but I think I missunderstood. ESP32 I2S should with auto make it mono when choosing only one channel

  • Hello again gain!

    I realize that the measurement of the FSYNCH was attrocious so here is a better one

  • Hi Christoffer,

    Thanks for the information.
    From the scope capture, C1 is BCLK and C2 is FSYNC, correct? Can you show a full cycle of C2? I just want to double check it runs 50%duty cycle. Your BCLK frequency is 3.072MHz?

    Regarding the interrupt flags, from register 0x24 it shows TDM clock error. Please make sure that both BCLK and FSYNC are running before enabling the device. Whenever the clocks stop the device goes into shutdown mode.

    Best regards,
    -Ivan Salazar
    Applications Engineer

  • Hello hello!

    Regarding the scope capture, I onle showed purely FSYNC (I might have misunderstood and thought you where only interested in that) so yes the orange channel 1 was indeed  FSYNC which has the values on the measurement as C2 aka the FSYNC frequency was measured to be 48002 kHz etc. Here is the scope from purely BCLK which is the orange and also has the measurement as C2



    Which has the frequency of 1.5370 MHz so rougly 50% of the 3.072MHz as you expected

    For the TDM error, I now make sure that the BCLK and FSYNC is going before enabling the amp and that did indeed clear the TDM error, so now the Latched interupts are

    {0x24, 0x00}

    {0x25, 0x00}

    {0x26, 0x11}

    {0x27, 0x80}

    {0x28, 0x00}

    {0x29, 0x40}

    My guess would be that the next step might have something to due with the 0x29 register which says there is an interrupt due to DMA Request to DSP lost flag? I realise that the last two registers aka 0x28 and 0x29 are not in the data sheet but they appear as valid registers when checking PPC3 (PurePath Console) register maps which calls them latched Interrupt Readback 4 and 5. I of course do not have direct acces to the amp from PPC3 but I do use it as a guide



  • Hi Christoffer,

    Perhaps we can first try to test the system with a simple configuration of the device in ROM mode. Let me share a new configuration script by tomorrow so you can give it a try.
    Did you generate the configuration script from your original post using PPC3?

    Best regards,
    -Ivan Salazar
    Applications Engineer

  • Hello again

    Yes thank you. I did generate it with PPC3, but I had to do some slight changes since the IRQZ pin is floating etc. I also tried activating the boost mode while monitoring the power consumption. 

    To be a bit more specific the configuration was generated while using the development kit and using an ESP32S3 as the I2C and I2S controllers, and I added the last {0x02,0x00} while writing the configuration to always have it active while testing.


  • Hi Christoffer,

    Did you used the ROM mode option at the End System Integration menu?

    Here's the script, I'm adding 0x02 command at the end as well to keep it similar.

    {
        { 0x00, 0x00 },
        { 0x7f, 0x00 },
        { 0x00, 0xfd },
        { 0x0d, 0x0d },
        { 0x32, 0x49 },
        { 0x3f, 0x21 },
        { 0x19, 0x80 },
        { 0x0d, 0x0d },
        { 0x5f, 0xc1 },
        { 0x00, 0x00 },
        { 0x0a, 0x03 },
        { 0x1a, 0xfc },
        { 0x1b, 0xa6 },
        { 0x1c, 0xdf },
        { 0x1d, 0xef },
        { 0x30, 0x19 },
        { 0x32, 0x80 },
        { 0x38, 0x00 },
        { 0x30, 0x19 },
        { 0x33, 0x34 },
        { 0x34, 0x4b },
        { 0x35, 0x84 },
        { 0x3c, 0x38 },
        { 0x00, 0x04 },
        { CFG_META_BURST, 4 },
        { 0x60, 0x04 },
        { 0xcc, 0xcc },
        { 0xcd, 0x00 },
        { CFG_META_BURST, 48 },
        { 0x14, 0x1c },
        { 0x94, 0x7a },
        { 0xe1, 0x1f },
        { 0xa3, 0xd7 },
        { 0x0a, 0x22 },
        { 0xb3, 0x33 },
        { 0x33, 0x25 },
        { 0xc2, 0x8f },
        { 0x5c, 0x28 },
        { 0xd1, 0xeb },
        { 0x85, 0x2b },
        { 0xe1, 0x47 },
        { 0xae, 0x2e },
        { 0xf0, 0xa3 },
        { 0xd7, 0x32 },
        { 0x00, 0x00 },
        { 0x00, 0x35 },
        { 0x0f, 0x5c },
        { 0x29, 0x38 },
        { 0x1e, 0xb8 },
        { 0x52, 0x3b },
        { 0x2e, 0x14 },
        { 0x7b, 0x04 },
        { 0xcc, 0xcc },
        { 0xcd, 0x00 },
        { 0x00, 0x03 },
        { CFG_META_BURST, 4 },
        { 0x5c, 0x1e },
        { 0x2e, 0x14 },
        { 0x7b, 0x00 },
        { CFG_META_BURST, 4 },
        { 0x60, 0x21 },
        { 0x3d, 0x70 },
        { 0xa4, 0x00 },
        { CFG_META_BURST, 4 },
        { 0x64, 0x24 },
        { 0x4c, 0xcc },
        { 0xcd, 0x00 },
        { CFG_META_BURST, 4 },
        { 0x68, 0x27 },
        { 0x5c, 0x28 },
        { 0xf6, 0x00 },
        { CFG_META_BURST, 4 },
        { 0x6c, 0x2a },
        { 0x6b, 0x85 },
        { 0x1f, 0x00 },
        { CFG_META_BURST, 4 },
        { 0x70, 0x2d },
        { 0x7a, 0xe1 },
        { 0x48, 0x00 },
        { CFG_META_BURST, 4 },
        { 0x74, 0x30 },
        { 0x8a, 0x3d },
        { 0x71, 0x00 },
        { CFG_META_BURST, 4 },
        { 0x78, 0x33 },
        { 0x99, 0x99 },
        { 0x9a, 0x00 },
        { CFG_META_BURST, 4 },
        { 0x7c, 0x36 },
        { 0xa8, 0xf5 },
        { 0xc3, 0x00 },
        { 0x00, 0x04 },
        { CFG_META_BURST, 4 },
        { 0x08, 0x39 },
        { 0xb8, 0x51 },
        { 0xec, 0x00 },
        { CFG_META_BURST, 4 },
        { 0x0c, 0x3c },
        { 0xc7, 0xae },
        { 0x14, 0x00 },
        { CFG_META_BURST, 4 },
        { 0x10, 0x3f },
        { 0xd7, 0x0a },
        { 0x3d, 0x00 },
        { CFG_META_BURST, 4 },
        { 0x54, 0x17 },
        { 0x99, 0x99 },
        { 0x9a, 0x00 },
        { CFG_META_BURST, 4 },
        { 0x6c, 0x00 },
        { 0x00, 0x00 },
        { 0x17, 0x00 },
        { 0x00, 0x00 },
        { 0x03, 0x20 },
        { 0x04, 0xc6 },
        { 0x0a, 0x03 },
        { 0x12, 0x12 },
        { 0x13, 0x76 },
        { 0x14, 0x01 },
        { 0x15, 0x2e },
        { 0x17, 0x0e },
        { 0x19, 0x00 },
        { 0x33, 0x34 },
        { 0x34, 0x4b },
        { 0x3b, 0x38 },
        { 0x3d, 0x08 },
        { 0x3e, 0x10 },
        { 0x3f, 0x00 },
        { 0x40, 0xb6 },
        { 0x00, 0x01 },
        { 0x08, 0x40 },
        { 0x00, 0x02 },
        { CFG_META_BURST, 4 },
        { 0x0c, 0x40 },
        { 0x00, 0x00 },
        { 0x00, 0x00 },
        { CFG_META_BURST, 4 },
        { 0x10, 0x03 },
        { 0x4a, 0x51 },
        { 0x6c, 0x00 },
        { 0x00, 0x04 },
        { CFG_META_BURST, 12 },
        { 0x74, 0x7f },
        { 0xfb, 0xb6 },
        { 0x14, 0x80 },
        { 0x04, 0x49 },
        { 0xed, 0x7f },
        { 0xf7, 0x6c },
        { 0x28, 0x00 },
        { 0x00, 0x02 },
        { CFG_META_BURST, 12 },
        { 0x68, 0x7f },
        { 0xfb, 0xb6 },
        { 0x14, 0x80 },
        { 0x04, 0x49 },
        { 0xed, 0x7f },
        { 0xf7, 0x6c },
        { 0x28, 0x00 },
        { CFG_META_BURST, 4 },
        { 0x14, 0x2d },
        { 0x6a, 0x86 },
        { 0x6f, 0x00 },
        { CFG_META_BURST, 4 },
        { 0x18, 0x47 },
        { 0x5c, 0x28 },
        { 0xf6, 0x00 },
        { CFG_META_BURST, 4 },
        { 0x1c, 0x16 },
        { 0x66, 0x66 },
        { 0x66, 0x00 },
        { CFG_META_BURST, 4 },
        { 0x20, 0x1a },
        { 0x66, 0x66 },
        { 0x66, 0x00 },
        { CFG_META_BURST, 4 },
        { 0x24, 0x08 },
        { 0x00, 0x00 },
        { 0x00, 0x00 },
        { CFG_META_BURST, 4 },
        { 0x28, 0x17 },
        { 0x33, 0x33 },
        { 0x33, 0x00 },
        { CFG_META_BURST, 4 },
        { 0x2c, 0x15 },
        { 0x99, 0x99 },
        { 0x9a, 0x00 },
        { 0x00, 0x05 },
        { CFG_META_BURST, 4 },
        { 0x24, 0x7f },
        { 0xfe, 0xfd },
        { 0x47, 0x00 },
        { CFG_META_BURST, 4 },
        { 0x2c, 0xfe },
        { 0xfe, 0xa4 },
        { 0xb5, 0x00 },
        { CFG_META_BURST, 4 },
        { 0x40, 0x00 },
        { 0x00, 0x03 },
        { 0x20, 0x00 },
        { CFG_META_BURST, 4 },
        { 0x44, 0x02 },
        { 0x46, 0xb4 },
        { 0xe4, 0x00 },
        { CFG_META_BURST, 4 },
        { 0x1c, 0x01 },
        { 0xc9, 0x24 },
        { 0x92, 0x00 },
        { CFG_META_BURST, 4 },
        { 0x20, 0x00 },
        { 0x12, 0x49 },
        { 0x25, 0x00 },
        { 0x00, 0x02 },
        { CFG_META_BURST, 4 },
        { 0x5c, 0x00 },
        { 0x01, 0x09 },
        { 0x45, 0x00 },
        { CFG_META_BURST, 4 },
        { 0x64, 0x00 },
        { 0x00, 0x12 },
        { 0xc0, 0x00 },
        { 0x00, 0x04 },
        { CFG_META_BURST, 4 },
        { 0x64, 0x00 },
        { 0x00, 0x00 },
        { 0x00, 0x00 },
        { CFG_META_BURST, 4 },
        { 0x40, 0x04 },
        { 0xcc, 0xcc },
        { 0xcd, 0x00 },
        { CFG_META_BURST, 4 },
        { 0x4c, 0x00 },
        { 0x00, 0x00 },
        { 0x00, 0x00 },
        { 0x00, 0x03 },
        { CFG_META_BURST, 4 },
        { 0x24, 0x39 },
        { 0x80, 0x00 },
        { 0x00, 0x00 },
        { CFG_META_BURST, 4 },
        { 0x18, 0x72 },
        { 0x14, 0x82 },
        { 0xc0, 0x00 },
        { CFG_META_BURST, 4 },
        { 0x1c, 0x00 },
        { 0x00, 0x00 },
        { 0x64, 0x00 },
        { CFG_META_BURST, 4 },
        { 0x20, 0x40 },
        { 0xbd, 0xb7 },
        { 0xc0, 0x00 },
        { CFG_META_BURST, 4 },
        { 0x28, 0x2d },
        { 0x6a, 0x86 },
        { 0x6f, 0x00 },
        { 0x00, 0x00 },
        { 0x04, 0xc6 },
        { 0x0a, 0x03 },
        { 0x31, 0x40 },
        {0x000x00},
        {0x7F0x00},
        {0x000x00},
        {0x020x00},
    };
    Best regards,
    -Ivan Salazar
    Applications Engineer
  • Helle again!

    Yes I did use ROM at the end of system integration. Even when I was working with the development board I could never get it to play in tuning mode.

    Regarding the configuration you sent, there is still no sound and the latched interupts are

    {0x24, 0x04}

    {0x25, 0x00}

    {0x26, 0x51}

    {0x27, 0x80}

    {0x28, 0x00}

    {0x29, 0x5C}


    I still make sure that both the FSYNC and BCLK is running before enabling the amp

  • I forgot to mention I also changed register 0x04 from 0x0C6 to 0xCE since there is no external pull up on the IRQZ pin (It however did nothing and the interupts are still the same)

  • HI Christoffer,

    It seems you're still getting the TDM clock error begin triggered.
    In order to check if the problem comes from the host that sends the clocks and data or the TAS device, is it possible that you take the EVM and use the clocks and data form the EVM to connect to the device on your system?

    We can also check why you couldn't get it working in tuning mode. Please confirm if you're using this EVM: TAS2X63EVM Evaluation board | TI.com

    Best regards,
    -Ivan Salazar
    Applications Engineer

  • Hi Ivan

    Well we are now back to the TDM clock error. When we tried to use my original config and I made sure that the clock and fsynch was on we did not get the TDM clock error (unless of course you still think that wqas the issue even if it was not in the interupt register).

    Sadly I cannot hook anything up with the TAS on our device, unless we desecrate the board so that is sadly not possible.

    Regarding the tuning mode, since the device is embedded it is not necesary to use tuning mode, and I would prefere if we could get the amp up and running. The development board I was using is TAS2563YBGEVM-DC Evaluation module

  • Hi Christoffer,

    We can go back to your configuration without TDM clock error.
    Does flag in reg 0x29 trigger every time you initialize the device?
    Also in that case, do you see the output Class-D switching at all?
    Please read register 0x11, does it show the expected FS_RATIO and FS_RATE values?

    Best regards,
    -Ivan Salazar
    Applications Engineer

  • Hello again!

    Sorry for the delay was busy with some other project
    If you feel more comfortable using a configuration that you wrote then let's stick to that one, primarely we just want it to play audio so there is no other requirements for the configuration

    Yes that flag in reg 0x29 does indeed trigger every time, and was also present in the configuration that you wrote

    I am not entirely sure what you mean by the out Class-D switching, the out pins show no data at all being transmitted to the loudspeaker if that is what you meant

    Regarding register 0x11 it shows an FS_RATIO of 32 (0x02) and an FS_RATE of  44.1/48 KHz (100b), which is what I expected it to show. Was that not the values you set in your configuration?

    Also if it is possible I am also willing to do a call where we look into it together if that is something you are okay with?

    With best regards
    Christoffer

  • Also I noticed in your configuration that you never set the register for samplerate and frame config aka 0x06. After setting this to the value of 0x49 the TDM clock error once again vanishes and I get the following values:

    {0x24, 0x00}

    {0x25, 0x00}

    {0x26, 0x11}

    {0x27, 0x80}

    {0x28, 0x00}

    {0x29, 0x40}

  • Hi Christoffer,

    Flag bit on reg 0x29 should be related to IVsense, can we check a few things:

    • Disconnect the speaker from the amplifier, and using an oscilloscope check either OUT_P or OUT_N. The output should be a PWM signal. If you connect the speaker back again and retry, is the PWM signal still there?
    • Do you have anything else connected at the output other than the speaker? Like inductors or capacitors? The schematic doesn't show anything but just want to doublecheck.
    • Try by changing the command for register 0x02 from the original 0x00 into 0x0c. Does that change anything?

    Let me reach out to you offline, we can setup a call tomorrow or early next week depending on the time difference.

    Best regards,
    -Ivan Salazar
    Applications Engineer

  • Hello again

    1) There is a PWM on the OUT_P/N both with the speaker on and off the board

    2) I just double checked, and there should be nothing on other than what is on the schematic

    3) sadly that had no effect

  • Hi Christoffer,

    Not sure whether this came before or after the emails.
    Please let me know if you still need help with device bring-up.

    Best regards,
    -Ivan Salazar
    Applications Engineer

  • This came before I got it to work, just forgot to add that statement here.

    Thank you for the provided support :D 

    With best regards
    Christoffer Møldrup