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SRC4392: 96KHz SAMPLE RATE

Henry Wang3
Genius 3745 points

Part Number: SRC4392

Hi Sir,

In the slave mode, How do set the registers to get the input and output to have the same sample rate?

My customer can use the 48KHz in the input and output, but they used the 96KHz in the input and only got the 48KHz in the output.

The register values are shown below.

  • 0
    TI__Mastermind 36471 points

    Hi Henry,

    In general when you have a device in Master mode, the device generates LRCLK & BCK from a reference clk such as SCK or MCLK or etc. On the other hand when you configure a device to be in Slave mode, then the user has to provide the LRCLK & BCK to the device.

    So in Slave mode, the sampling rate is whatever the users is providing to the chip. In contrast, In Master mode, the serial ports derive the LRCLK and BCK outputs from a selected master clock source,

    The following registre used to set the ports to M or S mode:

    Register 03: Port A Control Register 1 ,  Bit AM/S controls Port A Slave/Master Mode with same token Register 05 does the Slave/Master selection for Port B.

    In Slave mode, the minimum BCK is determined by the audio data word length x2 (since  there are two channels) per LRCLK period. So

    BCLK=LRCLK x 2  x  word length.  say for 96kHz and 32bits the provided BLK has to be 96000x2x32=3,072MHz

    Regards,

    Arash

  • 0 in reply to Arash Loloee
    Genius 3745 points

    Hi Sir,

    Thank you for your detailed explanation.

    But my customer designed the 2-channel input and only got the 48KHz in the single-end output, if they would like to get the 96KHz in the single-end output, does it need to increase the LRCLK to 192KHz, right?

  • 0 in reply to Henry Wang3
    TI__Guru 51200 points

    Hi Henry,

    Arash is out of office until Monday. He will address your question then.

    Thanks for your patience,

    Jeff McPherson

  • 0 in reply to Jeff McPherson
    Genius 3745 points

    Hi Sir,

    It's OK.

    The customer has another question, does the SRC4321 have a register to read the frequency values of LRCLK & BCK?

    They would like to check this frequency value and modify the TXDIV[1:0] in register 07.

  • 0 in reply to Henry Wang3
    TI__Guru 51200 points

    Hi Henry,

    Thanks for the additional question. Arash will answer both issues on Monday.

    Thanks for your patience,
    Jeff McPherson

  • 0 in reply to Henry Wang3
    TI__Mastermind 36471 points

    Hi Henry,

    From your post they are using the part as Slave mode, which means they send the I2S from an external source and thus whatever they select to send, the Part will receive it. With same token, if the output port is also in slave mode, then they have to provide the I2S clks.

    However, in master mode, the output sample rate are not provided externally by the user and you can set it. I am including few registers that they might find  useful to know.

    Register 03: Port A Control Register 1 , Bit AM/S      Port A Slave/Master Mode This bit is used to set the audio clock mode for Port At o either Slave or Master.

    Register 04: Port A Control Register 2  ,Bit BM/S       Port B Slave/Master Mode . This bit is used to set the audio clock mode for Port B to either Slave or Master.

    Register 06: Port B Control Register 2, bits  BDIV[1:0] Port B Master Mode Clock Divider are used to set the master clock divider for generating the LRCKB clock for Port B when configured for Master mode operation. BCKB is always set to 64 times the LRCKB clock rate in Master mode. 

    Register 07 (Transmitter Control Register 1) , bits   TXDIV[1:0]  which are Transmitter Master Clock Divider are used to select the Transmitter master clock divider, which determines the output frame rate.

    I am not clear on what it means by sending stereo in and getting single ended out, but if doubling the frequency is working for what they intended, then that is what it needs to be done. 

    I don't know of any register that can read back  the LRCCLK & BCK values, but   Register 32 can read the SRC Ratio .

    Regards,

    Arash