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TLV320DAC3101: Connecting, initializing, and playing I2S with ESP32 and TLV320DAC3101

Part Number: TLV320DAC3101

Hi

I want to connect the ESP32-WROVER-IE chip and the TLV320DAC3101 via I2C and I2S to play WAV sound files through SPL.

[I2S initiation]

void TLV320DAC3101::initI2S() {
   static const i2s_config_t i2s_config = {
      .mode = (i2s_mode_t)(I2S_MODE_MASTER | I2S_MODE_TX),
      .sample_rate = 44100,
      .bits_per_sample = I2S_BITS_PER_SAMPLE_16BIT, 
      .channel_format = I2S_CHANNEL_FMT_RIGHT_LEFT,
      .communication_format = I2S_COMM_FORMAT_I2S,
      .intr_alloc_flags = 0,
      .dma_buf_count = 8,
      .dma_buf_len = 64,
      .use_apll = false,
      .tx_desc_auto_clear = true
   };
   static const i2s_pin_config_t pin_config = {
      .bck_io_num = PIN_DAC_BCLK,
      .ws_io_num = PIN_DAC_WCLK,
      .data_out_num = PIN_DAC_DIN,
      .data_in_num = I2S_PIN_NO_CHANGE
   };
   i2s_driver_install(I2S_NUM, &i2s_config, 0, NULL);
   i2s_set_pin(I2S_NUM, &pin_config);
}

[tlv320dac3101 initiation]
int TLV320DAC3101::begin()
{
   initI2S();

   setRegister(0, 1, 1); // Soft reset
   vTaskDelay(pdMS_TO_TICKS(20));

   setRegister(0, 0x04, 0x07); // MCLK->BCLK, CODEC_CLKIN: PLL_CLK
   
   //	{ 1411200,  44100,	2, 32,   0,	128,   8,  2,	128,   8,  2},
   setRegister(0, 0x05, 0x92); // PLL P and R Values : P=1, R=2 *
   vTaskDelay(pdMS_TO_TICKS(10)); // PLL Power up time
   setRegister(0, 0x06, 0x20); // PLL J-Value : 32 *
   setRegister(0, 0x07, 0x00); // PLL D-HIGH-Value : 0 *
   setRegister(0, 0x08, 0x00); // PLL D-LOW-Value : 0 *
   setRegister(0, 0x0b, 0x88); // DAC NDAC_VAL : divide by 8
   setRegister(0, 0x0c, 0x82); // DAC MDAC_VAL : divide by 2
   setRegister(0, 0x0d, 0x00); // DAC DOSR_VAL MSB : 0 *
   setRegister(0, 0x0e, 0x80); // DAC DOSR_VAL LSB : 128 *
   setRegister(0, 0x1b, 0x00); // Codec Interface Control 1 : I2S, 16bits, BCLK/WCLK Input

   setRegister(0, 0x36, 0x02); // DIN (IN Pin) Control : enabled

   setRegister(0, 0x3c, 0x0b); // Processing Block : 25 

   setRegister(8, 0x01, 0x04); // DAC Coefficient RAM Control (continued) : 4 
   setRegister(1, 0x21, 0x00); // HP Output Drivers POP Removal Settings

   setRegister(0, 0x74, 0x00);

   setRegister(1, 0x23, 0x44); 

   setRegister(1, 0x20, 0xC6); 
   setRegister(1, 0x2A, 0x1C);
   setRegister(1, 0x2B, 0x1C);

   setRegister(1, 0x26, 0x80); 
   setRegister(1, 0x27, 0x80); 
   
   setRegister(0, 0x3F, 0xFD); 
   setRegister(0, 0x41, 0x00);
   setRegister(0, 0x42, 0x00);
   setRegister(0, 0x40, 0x00);

   vTaskDelay(pdMS_TO_TICKS(1000));

   return 1;
}
With the above setup, I confirmed that the register values of the TLV320DAC3101 change correctly.
I kept checking for signals by connecting pins to an oscilloscope,
and signals were detected on DIN, BCLK, and WCLK with accurate clock measurements.
However, no signal is detected on the SOUND pin. Could there be a problem with the settings or the circuit?
  • Hi Soonho,

    • Please confirm your WCLK and BCLK frequencies, is it 44.1kHz and 1.4112MHz?
    • Please confirm that WCLK and BCLK are up and running before initializing the DAC through I2C.
    • Your schematic shows only SPLP connected. This is not correct at least for SPLP/SPLM. Class-D is a differential output, so the load must be connected across SPLP and SPLM. If you use an oscilloscope connected to SPLP, do you see a switching PWM or no signal at all?
    • You're also enabling both left and right Class-D outputs, but seems you'll use only one of them?
    • Just to make sure it's not an issue, you should also supply SPRVDD same as you do for SPLVDD.

    Best regards,
    -Ivan Salazar
    Applications Engineer

  • [Please confirm your WCLK and BCLK frequencies, is it 44.1kHz and 1.4112MHz]

    => (use_apll: false->true), BCLK: 1,408,451 and WCLK: 43,860




    [Please confirm that WCLK and BCLK are up and running before initializing the DAC through I2C.]

    => process: esp32 I2S -> esp32 I2C -> DAC begin() -> play sound




    [Your schematic shows only SPLP connected. This is not correct at least for SPLP/SPLM. Class-D is a differential output, so the load must be connected across SPLP and SPLM. If you use an oscilloscope connected to SPLP, do you see a switching PWM or no signal at all?]

    => No signal at all. Then I will change the circuit.



    After transmitting the sound file via I2S and observing the DAC_DIN pin with an oscilloscope, I can see that data is being transmitted.

    However, when the positive line of the speaker is connected here and the negative line of the speaker is connected to GND,

    there is severe noise, but the sound file is being played. It's as if it is operating like PWM.

    When reading a WAV file and transmitting it via I2S in the same manner as the above code,

    could this be transmitted as PWM?

    Could it be that the DAC could not decode it because it is in PWM form?




    [You're also enabling both left and right Class-D outputs, but seems you'll use only one of them? Just to make sure it's not an issue, you should also supply SPRVDD same as you do for SPLVDD.]

    => Yes, I use one speaker so need just one. But for checking this issue, I will change the circuit.






    Best regards,

  • Hi Soonho,

    The output of Class-D is PWM signal, let's try to get the hardware connected such that speaker is properly connected across SPLP and SPLM. Then we can check if audio produced from the device is actually OK or not.

    Best regards,
    -Ivan Salazar
    Applications Engineer