TLV320AIC3101: Random No output due to wrong clock configuration

Hi,

If you are running 96KHz fs, you need to set ADC and DAC dual-rate mode to enable. This is in register 7 as shown below and keep fsref to 48KHz.

This is not an error. The fsref of 48KHz is a reference and needed for any fs that is multiple of 48KHz, the ratio is given in register 2.

Regards.

Hi Pdjuandi,

If running 96kHz fs but the register7 is configured as single-rate mode. How will the device operate? 

Thanks！

Rayna

Hello,

Peter is currently out of office. He will return on Monday and will get back to you then. Thank you for your patience!

Regards,
Sydney Northcutt 

Hi,

Any feedback here? Thanks!
Rayna

Please see the highlighted note below. For 96 kHz, you need to set the mode to dual-rate mode so the multiplier inside the device can support 96 kHz.

Regards.

Hi,

Any feedback here? Thanks!
Rayna

Hi Peter,

I understand that. The question here is 

if running at 96kHz but make a mistake to set the mode to single-rate mode. What will happen?

In customer side, they did this mistake and found the device randomly can't output any signal. So they were wondering what happen in this situation.

hope you could share some experience. Thanks!

Rayna

Hi,

Can't they reprogram or reconfigure the register? 

If this is not set, then the clocking is not correct as the bus was given a different rate than what was set.

The solution is set the correct configuration to what the host is providing.

Regards.

Hi Peter,

Yes, we have fixed this register mistake.

But customer want to figure out the internal working principles to understand what happen inside the device when they did the wrong configuration.

So I'm asking the result with 96kHz and single-rate mode. 

Thanks!

Rayna

Hi Ruixin,

What exactly will happen is unknown as it's dependent on the exact architecture, but the effect is unpredictable behavior. The dual-rate/single-rate control affects the oversampling rate of the ADC, meaning if you don't set the dual rate correctly, you violate the clocking limits of the ADC. Some devices it may look like you get half the frequency response (i.e. the nyquist frequency gets artificially lowered by half). Sometimes samples get dropped intermittently. Some devices may simply stop output if the clocking is violated, which may be what's happening here.

Best regards,
Jeff McPherson