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tlv320aic3204 on C5515 EVM

Max Zhegulin
Intellectual 420 points
Other Parts Discussed in Thread: TMS320C5515

Dear community,

 

I'm targeting aic3204 software examples on TMS320C5515 EVM.

In particulary I'm executing aic3204_loop_stereo_in2.c example from CCS4.1 installation directory. 

I have found signal attenuation after 6kHz. It's not clear from codec settings from aic3204_loop_stereo_in2.c example. 

For my future application 6kHz cut-off is undesirable, I need at least in 8kHz bandwidth.   

 

Thanks!

 

Max

  • 0
    Intellectual 420 points

    Very well! problem is resolved!

     

    If to look through PLL setting from aic3204_loop_stereo_in2.c example

     

        // PLL and Clocks config and Power Up  

        AIC3204_rset(  0, 0x00 );      // Select page 0

        AIC3204_rset( 27, 0x00 );      // BCLK and WCLK is set as i/p to AIC3204(Slave)

        AIC3204_rset(  4, 0x07 );      // PLL setting: PLLCLK <- BCLK and CODEC_CLKIN <-PLL CLK

        AIC3204_rset(  6, 8 );         // PLL setting: J

        AIC3204_rset(  7, 0 );         // PLL setting: HI_BYTE(D = 0)

        AIC3204_rset(  8, 0 );         // PLL setting: LO_BYTE(D) = 0

        // For 48 KHz sampling

      AIC3204_rset(  5, 0x92 );      // PLL setting: Power up PLL, P=1 and R=2

     

    and according to J.D, P and R prescaler values recalculate PLL_CLK ( in the same time CODEC_CLKIN ). 

    We get 25.008Mhz. 

    Then using this value to calculate ADC_FS and DAC_FS according to aic3204 datasheet page 80 we get.

    (NADC = NDAC, MADC=MDAC and ASOR =DSOR)

    ADC_FS = DAC_FS = ( 25.008 / ( 2 * 8 * 128) ) =  12.21kHz (!!!)

     

    It's not a surprise that in this case my bandwidth was 6kHz. 

     

    I was confused by comment.

        // For 48 KHz sampling

    I have spent much time without understanding why my filters do not work.

     

    Max